Mechanism for efficient low priority write draining

• US 6,523,098 B1
• Filed: 12/22/1999
• Issued: 02/18/2003
• Est. Priority Date: 12/22/1999
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Anderson, Andrew V.
• Primary Examiner(s): Hudspeth, David
• Assistant Examiner(s): TZENG, FRED
• Application Number:
  US09/469,676
• Time in Patent Office: 1,154 Days
• Field of Search: 711/111, 711/112, 711/144, 711/150, 711/141, 711/158, 711/163, 711/167, 711/168, 711/156, 711/169, 710/22, 710/52, 710/113, 710/244, 710/129, 710/111, 710/107, 712/6, 712/21, 712/220, 713/600, 714/49, 365/189.07, 709/235
• US Class Current: 711/158
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence

Abstract

In one embodiment, a method and apparatus for servicing a request for an opportunistic operation to a memory subsystem includes an enabling signal that is generated to service the request for the opportunistic operation according to any combination of the following information: availability of resources of the memory subsystem, status of pending requests for a high priority operation, and status of the request for the opportunistic operation.

Claims

1. A method, comprising generating an enabling signal to service a request for a low priority write operation according to any combination of availability of resources of a memory subsystem, status of pending requests for a high priority operation, and status of the request for the low priority write operation, as determined by counting a number of occurrences of requests for the low priority write operation, where the signal is generated when:

a. resources of the memory subsystem are available;

b. the pending requests for the high priority operation have been serviced; and

c. the number of occurrences exceeds a threshold value.

2. The method according to claim 1, wherein the availability of resources is determined by collecting and using depth value information from downstream elements.

3. The electronic system according to claim 1, wherein the threshold value comprises a predetermined value.

4. An apparatus, comprising:

a. a resource busy to determine availability of resources of a memory subsystem and to generate a first status signal;

b. a pending high-priority-operation detector to monitor pending requests for a high priority operation and to generate a second status signal;

c. an opportunistic-operation monitor to monitor requests for an opportunistic operation and to generate a third status signal; and

d. an arbiter, coupled to the resource busy detector, the pending high-priority-operation detector and the opportunistic-operation monitor, to generate an enabling signal to service a given request for an opportunistic operation according to the first, the second and third status signals.

5. The apparatus according to claim 4, wherein the resource busy detector collects and uses depth value information from downstream elements to indicate the availability of resources in the first status signal.

6. The apparatus according to claim 4, wherein the opportunistic-operation monitor comprises a depth counter to count a number of occurrences of requests for the opportunistic operation request.

7. The apparatus according to claim 6, wherein the arbiter generates the enabling signal when:

a. the first status signal indicates that resources are available;

b. the second status signal indicates that no requests for high priority operations are pending; and

c. the third status signal indicates that the number of occurrences exceeds a threshold value.

8. The apparatus according to claim 7, wherein the opportunistic operation refers to a low priority write operation.

9. The electronic system according to claim 7, wherein the threshold value comprises a predetermined value.

10. The apparatus according to claim 4, wherein the arbiter generates the enabling signal when:

a. the first status signal indicates resources are available; and

b. the second status signal indicates no requests for the high priority operation are pending.

11. The apparatus according to claim 10, wherein the high priority operation refers to read operations.

12. An electronic system, comprising:

a system bus;

a microprocessor, coupled to the system bus; and

a chipset component, coupled to the system bus and also coupled to a memory subsystem, wherein the chipset component further comprises;

a. a resource busy detector to determine availability of resources of the memory subsystem and to generate a first status signal;

b. a pending high-priority-operation detector to monitor pending request for a high priority operation and to generate a second status signal;

c. an opportunistic-operation monitor to monitor requests for an opportunistic operation and to generate a third status signal; and

d. an arbiter, coupled to the resource busy detector, the pending high-priority-operation detector and the opportunistic-operation monitor, to generate an enabling signal to service a given request for an opportunistic operation according to the first, the second and third status signals.

13. The electronic system according to claim 12, wherein the resource busy detector collects and uses depth value information from downstream elements to indicate the availability of resources in the first status signal.

14. The electronic system according to claim 12, wherein the opportunistic-operation monitor comprises a depth counter to count a number of occurrences of requests for the opportunistic operation.

15. The electronic system according to claim 14, wherein the arbiter generates the enabling signal when:

a. the first status signal indicates that resources are available;

b. the second status signal indicates that no requests for the high priority operation are pending; and

c. the third status signal indicates that the number of occurrences exceeds a threshold value.

16. The electronic system according to claim 15, wherein the opportunistic operation refers to a low priority write operation.

17. The electronic system according to claim 15, wherein the threshold value comprises a predetermined value.

18. The electronic system according to claim 12, wherein the arbiter generates the enabling signal when:

a. the first status signal indicates resources are available; and

b. the second status signal indicates no requests for the high priority operation are pending.

19. The electronic system according to claim 18, wherein the high priority operation refers to read operations.

20. A machine-readable medium having stored thereon data representing sequences of instructions, the sequences of instructions which, when executed by a processor, cause the processor to generate an enabling signal to service a request for a low priority write operation according to any combination of availability of resources of a memory subsystem, status of pending requests for a high priority operation, and status of the request for the low priority write operation by counting a number of occurrences of requests for the low priority write operation, where the signal is generated when:

a. resources of the memory subsystem are available;

b. the pending requests for the high priority operation have been serviced; and

c. the number of occurrences exceeds a threshold value.

21. The machine-readable medium according to claim 20, wherein the availability of resources is determined by collecting and using depth value information from downstream elements.

22. The machine-readable medium according to claim 20, wherein the threshold value comprises a predetermined value.

23. A method comprising:

a. determining if any pending requests exist;

b. if one or more pending requests exists, then determining if any of the one or more pending requests is a request for a high priority operation to a memory subsystem;

c. if any of the one or more pending requests is a request for the high priority operation, then selecting one of the pending requests for the high priority operation and issuing the selected pending request for the high priority operation to request queue;

d. if there are no pending requests for the high priority operation, then determining if there are any requests for an opportunistic operation; and

e. if there are one or more pending requests for the opportunistic operation, then selecting one of the one or more pending requests for the opportunistic operation and issuing the selected pending request for the opportunistic operation to the request queue if resources of the memory subsystem are available.

24. The method according to claim 23, wherein the issuing the selected pending request for the opportunistic operation to the request queue occurs if, additionally, the number of occurrences of the pending requests for the opportunistic operation exceeds a threshold.

25. The method according to claim 23, wherein the issuing the selected pending request for the high priority operation and the issuing the selected pending request for the opportunistic operation comprise generating an enabling signal.

26. A method comprising:

a. receiving a request for a low priority write operation;

b. issuing the request to a request queue by generating an enabling signal when;

i. resources of the memory subsystem are available;

ii. the pending requests for the high priority operation have been serviced; and

iii. a number of occurrences of the pending requests for the low