Bus system with a reduced number of lines
First Claim
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1. A method for reducing the number of lines in a bus system comprising the steps of:
- receiving, on a bus input, at least one data signal, a first clock signal, a first system potential, and a second system potential;
producing a second clock signal which is complementary to said first clock signal;
transmitting said data signals and said first and second clock signals over a bus;
locally producing, in one or more receiving units, first and second local power supply potentials from said first and second functional signals; and
powering said receiving unit exclusively from said first and second local power supply potentials.
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Abstract
In order to reduce the number of lines of a standard bus while, at the same time, preserving the compatibility of the communications protocol, the system uses a modified bus. The modification consists in eliminating two power supply lines and in creating a line assigned to a functional signal that is complementary to one of the functional signals of the system. The supply potentials are regenerated from the functional signal and the complementary signal. The disclosed system can be applied notably to systems using I2C buses such as systems using chip-card readers.
4 Citations
3 Claims
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1. A method for reducing the number of lines in a bus system comprising the steps of:
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receiving, on a bus input, at least one data signal, a first clock signal, a first system potential, and a second system potential;
producing a second clock signal which is complementary to said first clock signal;
transmitting said data signals and said first and second clock signals over a bus;
locally producing, in one or more receiving units, first and second local power supply potentials from said first and second functional signals; and
powering said receiving unit exclusively from said first and second local power supply potentials. - View Dependent Claims (2, 3)
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Specification
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Current AssigneeSGS-Thomson Microelectronics (STMicroelectronics NV)
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Original AssigneeSGS-Thomson Microelectronics (STMicroelectronics NV)
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InventorsTailliet, François, Bahout, Yvon
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Primary Examiner(s)WILEY, DAVID ARMAND
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Application NumberUS08/259,967Time in Patent Office3,171 DaysField of Search363/126, 395/325US Class Current713/300CPC Class CodesG06F 1/22 Means for limiting or contr...G06F 13/4072 Drivers or receivers G06F13...
