Flash EEprom system

• US 6,523,132 B1
• Filed: 09/08/2000
• Issued: 02/18/2003
• Est. Priority Date: 04/13/1989
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Harari, Eliyahou, Mehrotra, Sanjay, Norman, Robert D.
• Primary Examiner(s): HUA, LY
• Application Number:
  US09/657,482
• Time in Patent Office: 893 Days
• Field of Search: 714/8, 714/723, 714/710, 365/185.16, 365/185.25, 365/185.02, 365/230.06
• US Class Current: 714/6.13
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/312 In storage controller
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/068 : Hybrid storage device
• CPC Class Codes: G06F 3/0688 : Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/5621 : using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 : Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 : Erasing circuits
• CPC Class Codes: G11C 16/10 : Programming or data input circuits
• CPC Class Codes: G11C 16/16 : for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3436 : Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/344 : Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 : Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3454 : Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 : Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 : Multilevel programming verification
• CPC Class Codes: G11C 2211/5634 : Reference cells
• CPC Class Codes: G11C 2211/5643 : Multilevel memory comprising cache storage devices
• CPC Class Codes: G11C 2216/18 : Flash erasure of all the cells in an array, sector or block simultaneously
• CPC Class Codes: G11C 29/00 : Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/26 : Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/34 : Accessing multiple bits simultaneously
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/765 : in solid state disks
• CPC Class Codes: G11C 29/82 : for EEPROMs
• CPC Class Codes: G11C 7/1039 : using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 8/12 : Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Claims

1. A method of operating a memory that includes an array of non-volatile EEprom memory cells partitioned into a plurality of blocks that individually include a distinct group of memory cells that are erasable together as a unit, comprising:

maintaining a link between addresses of any unusable memory cell blocks and addresses of substitute usable memory cell blocks,

in response to a write request from a host system, initially writing new data intended for the EEprom memory cell array into a cache memory instead of the EEprom memory cell array,

thereafter, in response to additional space for new data being required in the cache memory, directing at least a portion of the data stored in the cache memory to be written into the EEprom memory cell array with an address including at least one of said memory cell blocks, and

writing said at least a portion of the data stored in the cache memory into the EEprom memory cell array by a method including;

if said at least one of said memory cell blocks is usable, writing said at least a portion of the data stored in the cache memory into said at least one of said memory cell blocks, and

if said at least one of said memory cell blocks is unusable, writing said at least a portion of the data stored in the cache memory into at least one of the substitute usable memory cell blocks that is linked with said at least one of said memory cell blocks.

2. The method of claim 1, wherein said at least a portion of the data stored in the cache memory that is written into the EEprom memory cell array includes that which has been stored in the cache memory for the longest time.

3. The method of claim 1, wherein the individual blocks of memory cells are operated with both user data and overhead data stored therein in non-overlapping portions of the individual blocks.

4. The method of claim 3, wherein overhead data stored in the individual blocks of memory include a characteristic of the individual block in which the user data and overhead data are stored.

5. The method of claim 3, wherein overhead data stored in the individual blocks of memory includes an error correction code for the user data stored in the same blocks.

6. The method of claim 3, wherein overhead data stored in the individual blocks of memory include an address corresponding to the block in which the overhead data are stored.

7. The method of claim 1, wherein writing at least a portion of the data stored in the cache memory into the EEprom memory cell array includes programming individual memory cells of the EEprom memory cell array into exactly two states in order to store exactly one bit of data per cell.

8. The method of claim 1, wherein writing at least a portion of the data stored in the cache memory into the EEprom memory cell array includes programming individual memory cells of the flash EEprom system into more than two states in order to store more than one bit of data per cell.

9. A method of a host system utilizing a mass data storage system to store data files, said mass data storage system including an array of non-volatile EEprom memory cells partitioned into a plurality of blocks that individually include a distinct group of memory cells that are erasable together as a unit, comprising:

writing individual new data files from the host to a cache memory provided as part of the mass data storage system without writing the new data files to the memory cell array,

when written into the cache memory, reading a data file requested by the host system from the cache memory rather than from the memory cell array,

thereafter writing a selected data file from the cache memory into the memory cell array, said writing including selecting at least one usable memory cell block into which the data file is written that includes either (a) the memory cell block whose address is mapped from a mass storage system address received from the host system, or (b) if the memory cell block whose address is mapped from the received mass storage system address is not usable, another memory cell block that is usable,

when written into the memory cell array, reading a data file requested by the host system from the memory cell array rather than from the cache memory.

10. The method of claim 9, wherein the individual new data files are written into a volatile random-access-memory as the cache memory.

11. The method of claim 9, wherein the individual new data files are written into a memory separate from the flash EEprom system as the cache memory.

12. The method of claim 9, wherein the mass data storage system is provided on a card that is electrically and mechanically removably connectable with the host computing system.

13. The method of claim 12, wherein the mass data storage system provides an ATA interface with the host computing system.

14. The method of claim 9, wherein selecting a data file and writing the selected data file to the EEprom memory cell array is caused to occur when additional space for new data files is required in the cache memory.

15. The method of claim 9, wherein the data file selected to be written into the memory cell array is selected based upon a length of time since the data file was last written into the cache memory.

16. The method of claim 9, wherein writing a new data file to the cache memory from the host occurs in less time than if written directly into the EEprom memory cell array from the host.

17. The method of claim 9, wherein the individual blocks of memory cells are operated with both user data and overhead data stored therein in non-overlapping portions of the individual blocks.

18. A bulk storage memory system that is connectable to a host system, said memory system comprising:

an array of non-volatile memory cells arranged to store in designated blocks thereof a given amount of user data and associated overhead data,

a cache memory separate from said non-volatile memory cell array, and

a controller connectable to said host system for controlling operation of the non-volatile memory cell array and the cache memory, said controller including;

an erasing circuit that causes all of the memory cells of one or more designated blocks of the array to be erased together,

an addressing circuit responsive to receipt of a mass memory storage block address from the host system to generate an address of at least one corresponding array block, the addressing circuit being responsive to a list of array blocks that have other array blocks substituted therefore to substitute at least one address of such other array blocks for the generated address of said at least one array block,

a first data transfer circuit responsive to the addressing circuit to execute an instruction from the host system to perform a designated one of (1) a data write operation by writing user data to the cache memory, or (2) a data read operation by reading addressed user data first from the cache memory, if stored therein, or from the array, if not stored in the cache memory, and

a second data transfer circuit that removes data from the cache by writing the data so removed into the array of non-volatile memory cells.

19. The memory system according to claim 18, wherein the second data transfer circuit removes data from the cache in response to additional space for new data being required in the cache memory.

20. The memory system according to claim 18, wherein the second data transfer circuit removes data from the cache that has been stored in the cache memory for a time longer than the remaining data therein.

21. The memory system according to claim 18, wherein the list of array blocks that have other array blocks substituted therefore includes inoperable or defective blocks.

22. The memory system according to claim 21, wherein the inoperable or defective blocks include blocks that contain a number of defective cells in excess of a preset number.

23. The memory system according to claim 18, wherein said given amount of user data is 512 bytes.

24. The memory system according to claim 18, wherein said bulk storage memory system is implemented in a single package that is removably connectable to the host system through an electrical connector.

25. The memory system according to claim 18, wherein the overhead data stored in an individual one of the memory cell array blocks includes an error correction code of the user data stored in said individual block.

26. The memory system according to claim 18, wherein the first and second data transfer circuits write data into the memory cell array with exactly two programmable states per memory cell storage element, thereby to store exactly one bit of data per storage element.

27. The memory system according to claim 18, wherein the first and second data transfer circuits write data into the memory cell array with more than two programmable states per memory cell storage element, thereby to store more than one bit of data per storage element.