Method for supply voltage drop analysis during placement phase of chip design

• US 6,523,154 B2
• Filed: 12/14/2000
• Issued: 02/18/2003
• Est. Priority Date: 12/14/2000
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: International Business Machines Corporation
• Inventors: Cohn, John M., Zuchowski, Paul S., Wemple, Ivan L., Venuto, James
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US09/737,012
• Publication Number:
  US 20020112212A1
• Time in Patent Office: 796 Days
• Field of Search: 716/1-21, 703/14-16
• US Class Current: 716/112
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A method of analyzing supply voltage drops in a power grid for distributing power to an integrated circuit chip during design. The method initially comprises providing a library of circuits for use in designing an integrated circuit chip and determining a supply current requirement and an operating voltage range for each circuit in the circuit library. The method then includes calculating an admittance matrix representing the power grid with a pre-specified array of circuit ports defined by intersection of the power grid and a modeling grid, assigning regions of the power grid to each of the ports, and placing a set of circuits from the circuit library in regions on the power grid. The method further includes calculating a total node current at each of the ports by summing current requirements of all of the circuits located in the regions, calculating a node voltage at each of the ports by solving a system of linear equations corresponding to the calculated admittance matrix, imposing a penalty to each node having a node voltage outside of a predetermined range, and calculating the node voltages and the penalties to a cost-based floorplanning/placement analysis tool.

Claims

1. A method of designing an integrated circuit within a power grid comprising:

characterizing circuits in a circuit library for supply currents and voltage ranges;

constructing a power grid model based on general power requirements of the integrated circuit under design;

calculating an impedance matrix representing impedance between ports in the power grid model;

assigning selected circuits from the library to the ports;

calculating current and voltage at each of the ports;

using a cost function, based on said calculated current and voltage, and on said characterized currents and voltage ranges, to calculate a cost of placement of the assigned circuits; and

perturbing the assignment of the circuits, if the cost of such placement does not meet design requirements.

2. The method of claim 1, wherein the current at each of the ports is calculated by summing current requirements of all of the circuits located in the region of each port.

3. The method of claim 2, wherein the voltage at each of the ports is calculated by solving a system of linear equations involving a power-grid resistor network and applied voltage and current sources, whose matrix representation has been reduced and pre-factorized to permit system solution via direct forward and/or backward substitution.

4. The method of claim 1, wherein each circuit in the circuit library is characterized to determine its average DC supply current requirement and power-supply voltage range for which it functions acceptably.

5. The method of claim 4, further including, for each circuit in the circuit library, tabulating current values which depend on relative placement and load to approximate the supply current dependence on output capacitance.

6. The method of claim 1, wherein the power grid model represents circuit ports defined by intersection of the power grid model and a physical power grid of an integrated circuit.

7. The method of claim 6, wherein the power grid model has a periodicity of a multiple of the periodicity of the physical power grid of the integrated circuit.

8. The method of claim 1, further including, after calculating the impedance matrix, assigning regions of the power grid to each of the ports.

9. The method of claim 1, further including, after calculating current and voltage at each port, imposing a penalty to each port having a node voltage outside of a predetermined range.

10. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for designing an integrated circuit within a power grid using a library of circuits, said method steps comprising:

characterizing circuits in the library for supply currents and voltage ranges;

constructing a power grid model based on general power requirements of the integrated circuit under design;

calculating an impedance matrix representing impedance between ports in the power grid model;

assigning selected circuits from the library to the ports;

calculating current and voltage at each of the ports;

using a cost function, based on said calculated current and voltage, and on said

characterized currents and voltage ranges, to calculate a cost of placement of the assigned circuits; and

perturbing the assignment of the circuits, if the cost of such placement does not meet design requirements.

11. The program storage device of claim 10 wherein, in the method steps, the current at each of the ports is calculated by summing current requirements of all of the circuits located in the region of the port.

12. The program storage device of claim 11 wherein, in the method steps, the voltage at each of the ports is calculated by solving a system of linear equations involving a power-grid resistor network and applied voltage and current sources, whose matrix representation has been reduced and pre-factorized to permit system solution via direct forward and/or backward substitution.

13. A computer program product comprising a computer usable medium having computer readable program code means embodied therein for designing an integrated circuit within a power grid, the computer program product utilizing a library of circuits for use in designing an integrated circuit chip, the computer readable program code means in said computer program product comprising:

computer readable program code means for characterizing the circuits in the library for supply currents and voltage ranges;

computer readable program code means for constructing a power grid model based on general power requirements of the integrated circuit under design;

computer readable program code means for calculating an impedance matrix representing impedance between ports in the power grid model;

computer readable program code means for assigning selected circuits from the library to the ports;

computer readable program code means for calculating current and voltage at each of the ports;

computer readable program code means for using a cost function, based on said calculated current and voltage, and on said characterized currents and voltage ranges, to calculate a cost of placement of the assigned circuits; and

computer readable program code means for perturbing the assignment of the circuits, if the cost of such placement does not meet design requirements.

14. The computer program product of claim 13, wherein the current at each of the ports is calculated by summing current requirements of all of the circuits located in the region of each port.

15. The computer program product of claim 14, wherein the current at each of the ports is calculated by multiplying a vector of node currents by the impedance matrix.