Wiring designing method for semiconductor integrated circuit

• US 6,523,158 B1
• Filed: 10/10/2000
• Issued: 02/18/2003
• Est. Priority Date: 10/12/1999
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Hidaka, Itsuo
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): LIN, SUN J
• Application Number:
  US09/684,335
• Time in Patent Office: 861 Days
• Field of Search: 716/10, 716/1-14
• US Class Current: 716/113
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

In a wiring designing method for a semiconductor integrated circuit, a signal line (201) is wired. Adjacent signal lines (204, 205), in which output ends (204o, 205o) are opened, are mounted adjacently to the signal line (201). A capacitance is calculated which are formed by the signal line (201) and the adjacent lines (204, 205). Line lengths (L2, L3) of the adjacent lines (204, 205) are adjusted in accordance with the capacitance. The capacitance is changed by the adjustment of the line lengths (L2, L3). Accordingly, it is possible to adjust the capacitance formed by the two signal lines adjacent to each other and a delay amount of the signal flowing through the signal line.

Claims

1. A wiring designing method for a semiconductor integrated circuit, comprising:

calculating a capacitance formed by a signal line and a fixed line which has at least one open end output without a termination and which is adjacent to said signal line;

adjusting a line length of said fixed adjacent line based on said calculated capacitance;

calculating a delay amount of a signal flowing through said signal line; and

calculating a delay difference indicative of a difference between the calculated delay amount and a predetermined delay amount,

wherein said adjusting step adjusts said line length of said adjacent line based on the calculated delay difference.

2. The wiring designing method according to claim 1, further comprising:

calculating a differential capacitance corresponding to said delay difference,

wherein said adjusting step adjusts said line length based on said differential capacitance and a distributed capacitance rate of said adjacent line.

3. The wiring designing method according to claim 2, wherein a control signal supplied to said adjacent line is determined based on a direction of a phase shift of the signal flowing through said signal line.

4. The wiring designing method according to claim 3, wherein when said direction of the phase shift indicates a delay of said signal flowing through said signal line, said control signal supplied to said adjacent line is set to a fixed potential.

5. The wiring designing method according to claim 3, wherein when said direction of the phase shift indicates an advance of said signal flowing through said signal line, said control signal supplied to said adjacent line is set to a first control signal having the same phase as said signal flowing through said signal line.

6. The wiring designing method according to claim 3, wherein when said direction of the phase shift indicates a delay of said signal flowing through said signal line, said control signal supplied to said adjacent line is set to a second control signal having an opposite phase to said signal flowing through said signal line.

7. A design support system for a semiconductor integrated circuit, comprising:

a routing tool which wires a signal line and a fixed line which has at least one open end output without a termination and which is adjacent to said signal line; and

a timing adjustment tool which determines a line length of said fixed adjacent line based on a delay amount of a signal flowing through said signal line, wherein said timing adjustment tool;

measures a delay amount of the signal flowing through said signal line;

calculates a delay difference indicative of a difference between the measured delay amount and a predetermined delay amount; and

adjusts said line length of said adjacent line based on the calculated delay difference.

8. The design support system according to claim 7, wherein the timing adjustment tool:

calculates a differential capacitance corresponding to said delay difference; and

adjusts said line length of the adjacent line based on said differential capacitance and a distributed capacitance rate of said adjacent line.

9. The design support system according to claim 8, wherein said timing adjustment tool determines a phase of a control signal supplied to said adjacent line based on a direction of a phase shift of the signal flowing through said signal line.

10. The design support system according to claim 9, wherein said timing adjustment tool, when said direction of the phase shift indicates a delay of said signal flowing through said signal line, sets the control signal supplied to said adjacent line at a fixed potential.

11. The design support system according to claim 9, wherein said timing adjustment tool, when said direction of the phase shift indicates an advance of said signal flowing through said signal line, sets the control signal supplied to said adjacent line at a first control signal having the same phase as said signal flowing through said signal line.

12. The design support system according to claim 9, wherein said timing adjustment tool, when said direction of the phase shift indicates a delay of said signal flowing through said signal line, sets the control signal supplied to said adjacent line at a second control signal having an opposite phase to said signal flowing through said signal line.

13. A wiring designing method for a semiconductor integrated circuit comprising:

calculating a capacitance formed by a signal line, a first line, and a second line, the first line and the second line both having at least one open end output without a termination and being adjacent to said signal line; and

adjusting a line length of the first line and adjusting a line length of the second line in order to adjust a delay amount of a signal flowing through the signal line based on said calculated capacitance, said adjustment being performed without re-routing said first and second lines.

14. A design support system for a semiconductor integrated circuit, comprising:

a routing tool which wires a signal line, a first line, and a second line, said first line and said second line both having at least one open end output without a termination and being adjacent to said signal line; and

a timing adjustment tool which determines a first line length of said first line and a second line length of said second line based on a delay amount of a signal flowing through said signal line, said determination being performed without re-routing said first and second lines.