Method of making a parallel capacitor laminate

• US 6,524,352 B2
• Filed: 01/09/2002
• Issued: 02/25/2003
• Est. Priority Date: 08/30/2000
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Lowell, Michael D., Sniezek, Joseph J., Lauffer, John M., Markovich, Voya R., Adae-Amoakoh, Sylvia
• Primary Examiner(s): NGUYEN, HA T
• Application Number:
  US10/043,830
• Publication Number:
  US 20020054471A1
• Time in Patent Office: 412 Days
• Field of Search: 361/301.3, 361/306.3, 29/250.3, 427/79, 427/80
• US Class Current: 29/25.03
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 1/053 the metal substrate being covered by an inorganic insulating layer
• CPC Class Codes: H05K 1/141 One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 2201/0175 Inorganic, non-metallic layer, e.g. resist or dielectric for printed capacitor
• CPC Class Codes: H05K 2201/0179 Thin film deposited insulating layer, e.g. inorganic layer for printed capacitor
• CPC Class Codes: H05K 2201/0338 Layered conductor, e.g. layered metal substrate, layered finish layer or layered thin film adhesion layer
• CPC Class Codes: H05K 2201/0919 Exposing inner circuit layers or metal planes at the side edge of the printed circuit board [PCB] or at the walls of large holes
• CPC Class Codes: H05K 2201/10378 Interposers
• CPC Class Codes: H05K 2203/0315 Oxidising metal
• CPC Class Codes: H05K 3/403 Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof H05K3/4092 takes precedence
• CPC Class Codes: H05K 3/445 having insulated holes or insulated via connections through the metal core
• CPC Class Codes: H05K 3/4608 comprising an electrically conductive base or core

Abstract

A parallel capacitor structure capable of forming an internal part of a larger circuit board or the like structure to provide capacitance therefore. Alternatively, the capacitor may be used as an interconnector to interconnect two different electronic components (e.g., chip carriers, circuit boards, and even semiconductor chips) while still providing desired levels of capacitance for one or more of said components. The capacitor includes at least one internal conductive layer, two additional conductor layers added on opposite sides of the internal conductor, and inorganic dielectric material (preferably an oxide layer on the second conductor layer'"'"'s outer surfaces or a suitable dielectric material such as barium titanate applied to the second conductor layers). Further, the capacitor includes outer conductor layers atop the inorganic dielectric material, thus forming a parallel capacitor between the internal and added conductive layers and the outer conductors.

Claims

1. A method of making a parallel capacitor laminate comprising:

providing a first electrically conductive layer having first and second opposing surfaces and at least one hole therein;

forming first and second layers of electrically conductive material on said first and second opposing surfaces of said first conductive layer, respectively and within said at least one hole;

forming first and second layers of inorganic dielectric material on said first and second layers of said electrically conductive material, respectively; and

forming third and fourth layers of electrically conductive material on said first and second layers of inorganic dielectric material, respectively, said third and fourth layers of electrically conductive material being electrically coupled to one another through said at least one hole, said first and second layers of electrically conductive material forming a substantially parallel capacitor with said third and fourth layers of electrically conductive material.

2. The method of claim 1 wherein said first electrically conductive layer is provided in rolled foil form.

3. The method of claim 1 further including providing holes in said first electrically conductive layer.

4. The method of claim 1 wherein said forming of said first and second layers of electrically conductive material is accomplished by sputtering or evaporation.

5. The method of claim 1 wherein said forming of said first and second layers of inorganic dielectric material is accomplished by anodization or sputtering or a combination of anodization and sputtering.

6. The method of claim 5 wherein said laminate is thermally annealed following said forming of said first and second layers of inorganic dielectric material.

7. The method of claim 1 wherein said forming of said third and fourth layers of electrically conductive material is accomplished by sputtering or plating or a combination of sputtering and plating.

8. The method of claim 1 further including patterning of said third and fourth layers of electrically conductive material to form a circuit pattern thereon.

9. The method of claim 8 wherein said patterning of said second and third layers of electrically conductive material is accomplished using photolithography processing.

10. The method of claim 1 further including forming a barrier layer on said first and second layers of inorganic dielectric material prior to said forming of said third and fourth layers of electrically conductive material.

11. The method of claim 1 further including electrically isolating said third and fourth layers of electrically conductive material.