Continuous movement scans of test structures on semiconductor integrated circuits

• US 6,524,873 B1
• Filed: 08/25/2000
• Issued: 02/25/2003
• Est. Priority Date: 12/14/1999
• Status: Expired due to Term

• Current Assignee: KLA-Tencor Corporation (KLA Corporation)
• Original Assignee: KLA-Tencor Corporation (KLA Corporation)
• Inventors: Walker, David J., Tsai, Bin-Ming Benjamin, Satya, Akella V. S., Adler, David L., Richardson, Neil
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): STEVENSON, ANDRE C
• Application Number:
  US09/648,094
• Time in Patent Office: 914 Days
• Field of Search: 438/14, 324/751, 324/750
• US Class Current: 438/18
• CPC Class Codes: G01N 21/66 electrically excited, e.g. electroluminescence
• CPC Class Codes: G01N 21/956 Inspecting patterns on the surface of objects contactless testing of electronic circuits G01R31/308; testing currency G07D; manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/307 of integrated circuits
• CPC Class Codes: H01J 2237/2817 Pattern inspection
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

Disclosed is, a method for detecting electrical defects on test structures of a semiconductor die. The semiconductor die includes a plurality of electrically-isolated test structures and a plurality of non-electrically-isolated test structures. Voltages are established for the plurality of electrically-isolated test structures. These voltages are different than the voltages of the plurality of non-electrically-isolated test structures. A region of the semiconductor die is continuously inspected in a first direction thereby obtaining voltage contrast data indicative of whether there are defective test structures. The voltage contrast data is analyzed to determine whether there are one or more defective test structures.

Claims

1. A method for detecting electrical defects on test structures of a semiconductor die, the semiconductor die comprising a plurality of first test structures that are designed to have a first voltage potential during a voltage contrast inspection and a plurality of second test structures that are designed to have a second voltage potential during a voltage contrast inspection, wherein the first voltage potential differs from the second voltage potential, comprising:

a. with a charged particle beam, inspecting a region of the semiconductor die continuously in a first direction so that a plurality of field of views of portions of the region are continuously obtained, thereby obtaining voltage contrast data from the multiple field of views indicative of whether there are defective test structures in the region; and

b. analyzing the voltage contrast data to determine whether there are one or more defective test structures.

2. The method of claim 1 wherein the at least one defect detected in step a is located outside the region inspected in step a.

3. The method of claim 1 wherein the charged particle beam is an electron beam.

4. The method of claim 2 comprising the further step c of inspecting the semiconductor die in a second direction to locate at least one defect detected in step b.

5. The method of claim 1 wherein step b comprises comparing voltage contrast data obtained in step a to a database.

6. The method of claim 5 wherein the database comprises expected voltage contrast images.

7. The method of claim 1 wherein step b comprises comparing voltage contrast data to a truth table.

9. The method of claim 1 wherein steps a and b are performed simultaneously.

10. The method of claim 4 wherein steps a and b are interrupted when a defective structure is detected.

11. The method of claim 10 wherein step c is taken directly after steps a and b are interrupted.

12. The method of claim 11 wherein steps a and b are resumed after step c is completed.

13. The method of claim 1 wherein the region is predetermined.

16. The method of claim 1 wherein the semiconductor die rests on a stage and step a comprises moving the stage.

17. The method of claim 1 wherein the semiconductor die rests on a stage under a column through which the particle beam travels and step a comprises moving the column relative to the stage.

18. The method of claim 16 wherein step a further comprises moving a particle beam.

19. The method of claim 18 wherein the moving the particle beam in step a comprises moving the particle beam back and forth in the second direction.

20. The method of claim 19 wherein the combined motion of the particle beam and stage in step a forms a serpentine pattern over the semiconductor die.

21. The method of claim 20 wherein the beam and stage are moved relative to the semiconductor die to produce the serpentine pattern.

22. The method of claim 1 wherein the region is substantially rectangular.

23. The method of claim 22 wherein the region is substantially elongated in the first direction.

8. The method of claim 8 wherein the truth table indicate which test structures are expected to appear dark and which are expected to appear light.

14. A method for detecting electrical defects on test structures of a semiconductor die, the semiconductor die comprising a plurality of electrically-isolated test structures and a plurality of non-electrically-isolated test structures, comprising:

a. establishing for the plurality of electrically-isolated test structures voltages different than the voltages of the plurality of non-electrically-isolated test structures;

b. inspecting a region of the semiconductor die continuously in a first direction, thereby obtaining voltage contrast data indicative of whether there are defective test structures;

c. analyzing the voltage contrast data to determine whether there are one or more defective test structures; and

d. inspecting the semiconductor die in a second direction to locate at least one defect detected in step c,

wherein steps b and c are performed simultaneously and are interrupted when a defective structure is detected,

wherein step d is taken directly after steps b and c are interrupted,

wherein steps b and c are resumed after step d is completed, and

wherein step b is completed for the entirety of the region before step d.

15. A method for detecting electrical defects on test structures of a semiconductor die, the semiconductor die comprising a plurality of electrically-isolated test structures and a plurality of non-electrically-isolated test structures, comprising:

a. establishing for the plurality of electrically-isolated test structures voltages different than the voltages of the plurality of non-electrically-isolated test structures; and

b. inspecting a region of the semiconductor die continuously in a first direction, thereby obtaining voltage contrast data indicative of whether there are defective test structures;

c. analyzing the voltage contrast data to determine whether there are one or more defective test structures; and

d. inspecting the semiconductor die in a second direction to locate at least one defect detected in step c,

wherein the region is predetermined, and

wherein step b is completed for the entirety of the region before step d.