Semiconductor device and method of fabricating the same
First Claim
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1. A method of fabricating a semiconductor device comprising the steps of:
- forming a semiconductor layer over a substrate having an insulation surface;
patterning said semiconductor layer to form at least a first and a second island semiconductor layers;
forming a gate insulation film in contact with said first and second island semiconductor layers;
adding an impurity element of one conductivity type into a selected region of said first island semiconductor layer, and forming a second impurity region;
forming a first conductor layer in contact with said gate insulation film after adding the impurity element of the one conductivity type;
forming a second gate electrode overlapping with said second island semiconductor layer by patterning said first conductor layer;
adding an impurity element of a conductivity type opposite to said one conductivity type into a selected region of said second island semiconductor layer, and forming a third impurity region;
forming a first gate electrode overlapping with said first island semiconductor layer by patterning said first conductor layer after adding the impurity element of the conductivity type opposite to said conductivity type; and
adding an impurity element of said one conductivity type into a selected region of said first island semiconductor layer, and forming a first impurity region.
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Abstract
Reliability of crystalline TFTs is improved in a large area integrated circuit typified by an active matrix type liquid crystal display device. In TFTs having an LDD structure, a region whose LDD region overlaps with a gate electrode and a region not overlapping with the gate electrode are fabricated inside one TFT. To accomplish this structure, n-channel TFTs are fabricated in non-self-alignment whereas p-channel TFTs are fabricated in self-alignment.
210 Citations
78 Claims
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1. A method of fabricating a semiconductor device comprising the steps of:
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forming a semiconductor layer over a substrate having an insulation surface;
patterning said semiconductor layer to form at least a first and a second island semiconductor layers;
forming a gate insulation film in contact with said first and second island semiconductor layers;
adding an impurity element of one conductivity type into a selected region of said first island semiconductor layer, and forming a second impurity region;
forming a first conductor layer in contact with said gate insulation film after adding the impurity element of the one conductivity type;
forming a second gate electrode overlapping with said second island semiconductor layer by patterning said first conductor layer;
adding an impurity element of a conductivity type opposite to said one conductivity type into a selected region of said second island semiconductor layer, and forming a third impurity region;
forming a first gate electrode overlapping with said first island semiconductor layer by patterning said first conductor layer after adding the impurity element of the conductivity type opposite to said conductivity type; and
adding an impurity element of said one conductivity type into a selected region of said first island semiconductor layer, and forming a first impurity region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A method of manufacturing a semiconductor device comprising:
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forming at least first and second semiconductor layers on an insulating surface;
forming a gate insulation film on the first and second semiconductor layers;
forming a mask over a selected portion of the second semiconductor layer;
introducing a first impurity having a first conductivity type into the second semiconductor layer in accordance with the mask to form a pair of first impurity regions;
forming a conductive film on the gate insulating film after removing the mask;
patterning the conductive film to form a first gate electrode over the first semiconductor layer with the gate insulating film interposed therebetween;
introducing a second impurity having an opposite conductivity type to the first conductivity type into the first semiconductor layer with the first gate electrode used as a mask, thereby forming a pair of second impurity regions in the first semiconductor layer;
patterning the conductive film to form a second gate electrode over the second semiconductor layer with the gate insulation film interposed therebetween, after introducing the second impurity into the first semiconductor layer;
covering the second gate electrode with a second mask;
introducing a third impurity having a same conductivity type as the first conductivity type into the second semiconductor layer in accordance with the second mask, thereby, forming a third pair of impurity regions in the second semiconductor layer. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
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39. A method of manufacturing a semiconductor device comprising:
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forming at least first and second semiconductor layers on an insulating surface;
forming a gate insulation film on the first and second semiconductor layers;
forming a mask over a selected portion of the second semiconductor layer;
introducing a first impurity having a first conductivity type into the second semiconductor layer in accordance with the mask to form a pair of first impurity regions while the first impurity is not introduced into the first semiconductor layer;
forming a conductive film on the gate insulating film after removing the mask;
patterning the conductive film to form a first gate electrode over the first semiconductor layer with the gate insulating film interposed therebetween;
introducing a second impurity having an opposite conductivity type to the first conductivity type into the first semiconductor layer with the first gate electrode used as a mask, thereby forming a pair of second impurity regions in the first semiconductor layer wherein a portion of the conductive film covers the second semiconductor layer so that the second impurity is not introduced into the second semiconductor layer;
patterning the portion of the conductive film to form a second gate electrode over the second semiconductor layer with the gate insulation film interposed therebetween, after introducing the second impurity into the first semiconductor layer;
covering the second gate electrode with a second mask;
introducing a third impurity having a same conductivity type as the first conductivity type into the second semiconductor layer in accordance with the second mask, thereby, forming a third pair of impurity regions in the second semiconductor layer wherein the third impurity is not introduced into the first semiconductor layer. - View Dependent Claims (40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58)
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59. A method of manufacturing a semiconductor device comprising:
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forming at least first and second semiconductor layers on an insulating surface;
forming a gate insulation film on the first and second semiconductor layers;
forming a mask over a selected portion of the second semiconductor layer;
introducing a first impurity having a first conductivity type into the second semiconductor layer in accordance with the mask to form a pair of first impurity regions;
forming a conductive film on the gate insulating film after removing the mask;
patterning the conductive film to form a first gate electrode over the first semiconductor layer with the gate insulating film interposed therebetween;
introducing a second impurity having an opposite conductivity type to the first conductivity type into the first semiconductor layer with the first gate electrode used as a mask, thereby forming a pair of second impurity regions in the first semiconductor layer;
patterning the conductive film to form a second gate electrode over the second semiconductor layer with the gate insulation film interposed therebetween, after introducing the second impurity into the first semiconductor layer wherein the second gate electrode partly overlaps the pair of first impurity regions;
covering the second gate electrode with a second mask wherein the second mask extends beyond side edges of the second gate electrode;
introducing a third impurity having a same conductivity type as the first conductivity type into the second semiconductor layer in accordance with the second mask, thereby, forming a third pair of impurity regions in the second semiconductor layer. - View Dependent Claims (60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78)
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Specification
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Current AssigneeSemiconductor Energy Laboratory Co., Ltd.
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Original AssigneeSemiconductor Energy Laboratory Co., Ltd.
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InventorsKoyama, Jun, Yamazaki, Shunpei
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Primary Examiner(s)Chaudhuri, Olik
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Assistant Examiner(s)Ha, Nathan W.
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Application NumberUS09/471,359Publication NumberTime in Patent Office1,160 DaysField of Search438/150, 438/166, 438/149, 257/72, 257/347, 257/219, 257/350, 257/59US Class Current438/149CPC Class CodesH01L 2029/7863 with an LDD consisting of m...H01L 27/1214 comprising a plurality of T...H01L 27/1251 comprising TFTs having a di...H01L 27/127 with a particular formation...H01L 27/1288 employing particular maskin...H01L 29/66757 Lateral single gate single ...H01L 29/78621 with LDD structure or an ex...H01L 29/78627 with a significant overlap ...H01L 29/78645 with multiple gate
