Controlled gate length and gate profile semiconductor device and manufacturing method therefor

• US 6,524,916 B1
• Filed: 05/01/2002
• Issued: 02/25/2003
• Est. Priority Date: 01/29/2000
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Scholer, Thomas C., Yu, Allen S., Steffan, Paul J.
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): Rao, Shrinivas H.
• Application Number:
  US10/137,568
• Time in Patent Office: 300 Days
• Field of Search: 438/270, 438/271, 438/585, 438/587, 438/588, 438/592, 257/288, 257/331, 257/336, 257/412
• US Class Current: 438/270
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

An ultra-large scale integrated circuit semiconductor device is provided which has inverted trapezoidal gates with LDD structures having gradual doping profiles and salicided for contacts. The structures are manufactured on a substrate by forming a barrier layer over the substrate, forming a gate layer over the barrier layer, forming inverted trapezoidal gate trenches into the gate layer that are a function of the thickness of the gate layer, depositing a gate dielectric in the inverted trapezoidal gate trenches on the substrate, forming polysilicon gates in the inverted trapezoidal gate trenches, removing the gate layer and the barrier layer to define gate spacers, implanting the substrate around the gate spacers with a dopant to form source/drain extension junctions, and preparing the source/drain extension junctions and the gates for conductive connections.

Claims

1. A method of manufacturing a CMOS semiconductor comprising:

providing a substrate;

forming first and second gate dielectrics on the substrate;

forming first and second trapezoidal semiconductor gates respectively disposed on the first and second gate dielectrics, the first and second trapezoidal semiconductor gate dielectrics respectively having thickness T1 and T2, first and second top widths, and bottom widths W3 and W4 where W3 and W4 are respectively smaller than the first and second top widths wherein;

the first and second top widths are respectively directly proportional to T1 and T2 when W3 and W4 are equal dimensions,

W3 and W4 are respectively inversely proportional to T1 and T2 when the first and second top widths are equal dimensions, and

the first and second top widths are equal and W3 and W4 are equal when T1 and T2 are equal dimensions;

forming gate spacers around the first and second trapezoidal semiconductor gates;

forming source/drain junction regions in the substrate under the gate spacers and self-aligned with the gate dielectrics;

forming contact areas on a source/drain junction regions adjacent to and coplanar with the gate spacers;

forming secondary spacers adjacent the gate spacers; and

forming deep source/drain junction regions in the substrate under the contact areas adjacent the secondary spacers and self-aligned with the secondary spacers.

2. The method as claimed in claim 1 including:

forming deep source/drain junction regions in the substrate under the contact areas connected to the source/drain junction regions; and

forming trench isolations disposed in the substrate around the deep source/drain junction regions.

3. The method as claimed in claim 1 wherein:

forming the gate spacers includes an oxide below a nitride.

4. A method of manufacturing a CMOS semiconductor device comprising:

providing a semiconductor substrate;

forming first and second gate oxide layers on the semiconductor substrate;

forming first and second trapezoidal polysilicon gates disposed on the first and second gate oxide layers, the first and second trapezoidal polysilicon gates respectively having thickness T1 and T2, first and second top widths, and bottom widths W3 and W4 where W3 and W4 are respectively smaller than the first and second top widths wherein;

the first and second top widths are respectively directly proportional to T1 and T2 when W3 and W4 are equal dimensions,

the first and second top widths are respectively inversely proportional to T1 and T2 when the first and second top widths are equal dimensions, and

the first and second top widths are equal and W3 and W4 are equal when T1 and T2 are equal dimensions;

forming gate spacers around the fist and second trapezoidal polysilicon gates;

forming lightly doped source/drain extension junction regions in the semiconductor substrate under the spacer and self-aligned with the gate oxide layers;

forming salicided contact areas above the doped source/drain extension junction adjacent and coplanar with the gate spacer;

forming secondary spacers adjacent to the gate spacers; and

forming heavily doped source/drain regions adjacent in the substrate directly under and contacting the salicided contact area adjacent the secondary spacer and self-aligned with the secondary spacers.

5. The method as claimed in claim 4 including:

forming trench isolations disposed in the substrate around the lightly doped source/drain extension junction regions.

6. The method as claimed in claim 4 wherein:

forming the gate spacers forms an oxide below a nitride; and

forming trench isolations forms an oxide.