High density flash EEPROM array with source side injection

• US 6,525,368 B1
• Filed: 06/27/2001
• Issued: 02/25/2003
• Est. Priority Date: 06/27/2001
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Fastow, Richard
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): SMITH, BRADLEY
• Application Number:
  US09/892,685
• Time in Patent Office: 608 Days
• Field of Search: 257/314, 257/315, 257/316, 257/321, 257/326, 257/296
• US Class Current: 257/314
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A flash electrically eraseable programmable read only memory (EEPROM) includes a plurality of flash memory cells formed on a semiconductor substrate, the plurality of memory cells being arranged in a matrix of m rows and n columns. The memory cells in each column are connected in series and include a drain coupled to a common bit line. In addition, the EEPROM includes a plurality of trenches formed in the semiconductor substrate, each of the plurality of trenches being formed between a corresponding pair of the n columns of memory cells. Moreover, the EEPROM includes a plurality of transistors formed at least in part in a corresponding sidewall of the plurality of trenches, each of the plurality of transistors connecting a source of a corresponding one of the memory cells to a Vss supply voltage.

Claims

1. A flash electrically eraseable programmable read only memory (EEPROM), comprising:

a plurality of flash memory cells formed on a semiconductor substrate, the plurality of memory cells being arranged in a matrix of m rows and n columns, wherein the memory cells in each column are connected in series and include a drain coupled to a common bit line;

a plurality of trenches formed in the semiconductor substrate, each of the plurality of trenches being formed between a corresponding pair of the n columns of memory cells; and

a plurality of transistors formed at least in part in a corresponding sidewall of the plurality of trenches, each of the plurality of transistors connecting a source of a corresponding one of the memory cells to a Vss supply voltage.

2. The EEPROM of claim 1, wherein the source and drain of the memory cells have a dopant having a first conductivity and a channel of the memory cells has a dopant having a second conductivity different from the first conductivity, and a bottom of each of the plurality of trenches includes a dopant of the first conductivity.

3. The EEPROM of claim 2, wherein each of the plurality of transistors includes a source formed in the bottom of the corresponding trench.

4. The EEPROM of claim 3, wherein each of the plurality of transistors includes a drain formed in a region of the source of the corresponding one of the memory cells.

5. The EEPROM of claim 2, wherein the bottom of each trench is coupled to the Vss supply voltage.

6. The EEPROM of claim 1, wherein the EEPROM includes a plurality of word lines each extending along a corresponding row of the memory cells and being operative to select simultaneously each of the memory cells in the corresponding row;

and

a plurality of control lines each extending between and parallel to a corresponding pair of the word lines, the control lines each being operative to control the conductivity of the transistors connected to the memory cells selected by the pair of word lines adjacent the control line.

7. The EEPROM of claim 6, wherein the source and drain of the memory cells have a dopant having a first conductivity and a channel of the memory cells has a dopant having a second conductivity different from the first conductivity, and a bottom of each of the plurality of trenches includes a dopant of the first conductivity.

8. The EEPROM of claim 7, wherein each of the plurality of transistors includes a source formed in the bottom of the corresponding trench.

9. The EEPROM of claim 8, wherein each of the plurality of transistors includes a drain formed in a region of the source of the corresponding one of the memory cells.

10. The EEPROM of claim 7, wherein the bottom of each trench is coupled to the Vss supply voltage.