Self-aligned split-gate flash memory cell and its contactless flash memory arrays
First Claim
1. A self-aligned split-gate flash memory cell having a single-side dish-shaped floating gate structure, comprising:
- a semiconductor substrate of a first conductivity type having an active region isolated by two parallel shallow-trench-isolation (STI) regions, wherein each of said two parallel STI regions is filled with a first raised field-oxide layer;
a cell region being formed on said semiconductor substrate and divided into three regions;
a common-source region, a gate region, and a common-drain region, wherein said gate region is located between said common-source region and said common-drain region;
said common-source region comprises a first sidewall dielectric spacer being formed over a sidewall of said gate region and on a portion of a first flat bed being formed by a shallow heavily-doped source diffusion region formed within a common-source diffusion region of a second conductivity type in said active region and two etched first raised field-oxide layers in said two parallel STI regions;
said common-drain region comprises a second sidewall dielectric spacer being formed over another sidewall of said gate region and on a portion of a second flat bed being formed by a shallow heavily-doped drain diffusion region formed within a common-drain diffusion region of said second conductivity type in said active region and two etched second raised field-oxide layers in said two parallel STI regions; and
said gate region comprises a single-side dish-shaped floating-gate structure being formed on a first gate-dielectric layer;
a first intergate-dielectric layer being formed over said single-side dish-shaped floating-gate structure;
a second intergate-dielectric layer being formed over an inner sidewall of said single-side dish-shaped floating-gate structure and its tip portion; and
a planarized control/select-gate conductive layer having a portion formed at least on a second gate-dielectric layer, said second intergate-dielectric layer, said first intergate-dielectric layer, and a portion of nearby said first/second raised field-oxide layers.
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Abstract
A self-aligned split-gate flash memory cell of the present invention comprises a single-side dish-shaped floating-gate structure being formed on a first gate-dielectric layer with a first intergate-dielectric layer being formed on its top portion and a second intergate-dielectric layer being formed on its inner sidewall and tip portion; a planarized control/select-gate conductive layer being at least formed over a second gate-dielectric layer and the first/second intergate-dielectric layers; and a common-source diffusion region and a common-drain diffusion region being implanted by aligning to the planarized control/select-gate conductive layer. The self-aligned split-gate flash memory cells are configured into two contactless array architectures: a contactless NOR-type flash memory array and a contactless parallel common-source/drain conductive bit-lines flash memory array.
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Citations
20 Claims
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1. A self-aligned split-gate flash memory cell having a single-side dish-shaped floating gate structure, comprising:
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a semiconductor substrate of a first conductivity type having an active region isolated by two parallel shallow-trench-isolation (STI) regions, wherein each of said two parallel STI regions is filled with a first raised field-oxide layer;
a cell region being formed on said semiconductor substrate and divided into three regions;
a common-source region, a gate region, and a common-drain region, wherein said gate region is located between said common-source region and said common-drain region;
said common-source region comprises a first sidewall dielectric spacer being formed over a sidewall of said gate region and on a portion of a first flat bed being formed by a shallow heavily-doped source diffusion region formed within a common-source diffusion region of a second conductivity type in said active region and two etched first raised field-oxide layers in said two parallel STI regions;
said common-drain region comprises a second sidewall dielectric spacer being formed over another sidewall of said gate region and on a portion of a second flat bed being formed by a shallow heavily-doped drain diffusion region formed within a common-drain diffusion region of said second conductivity type in said active region and two etched second raised field-oxide layers in said two parallel STI regions; and
said gate region comprises a single-side dish-shaped floating-gate structure being formed on a first gate-dielectric layer;
a first intergate-dielectric layer being formed over said single-side dish-shaped floating-gate structure;
a second intergate-dielectric layer being formed over an inner sidewall of said single-side dish-shaped floating-gate structure and its tip portion; and
a planarized control/select-gate conductive layer having a portion formed at least on a second gate-dielectric layer, said second intergate-dielectric layer, said first intergate-dielectric layer, and a portion of nearby said first/second raised field-oxide layers.- View Dependent Claims (2, 3, 4, 5)
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6. A contactless NOR-type self-aligned split-gate flash memory array, comprising:
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a semiconductor substrate of a first conductivity type having a plurality of active regions and a plurality of parallel shallow-trench-isolation (STI) regions formed alternately, wherein each of the plurality of parallel STI regions is filled with a first raised field-oxide layer;
a plurality of common-source regions and a plurality of virtual-gate regions being formed alternately and transversely to the plurality of parallel STI regions, wherein each of the plurality of virtual-gate regions includes a pair of self-aligned split-gate regions being located in each side portion and a common-drain region being located between the pair of self-aligned split-gate regions;
each of the plurality of common-source regions comprises a pair of first sidewall dielectric spacers being formed over each sidewall of nearby said virtual-gate regions and on a portion of a first flat bed being alternately formed by an etched first raised field-oxide layer in said parallel STI region and a shallow heavily-doped source diffusion region formed within a common-source diffusion region of a second conductivity type in said active region;
a common-source conductive bus line being formed over said first flat bed between the pair of first sidewall dielectric spacers; and
a first planarized thick-oxide layer being formed over said common-source conductive bus line;
said common-drain region comprises a pair of second sidewall dielectric spacers being formed over each sidewall of nearby self-aligned split-gate regions and on a portion of a second flat bed being alternately formed by an etched second raised field-oxide layer in said parallel STI region and a shallow heavily-doped drain diffusion region formed within a common-drain diffusion region of said second conductivity type in said active region;
a plurality of planarized common-drain conductive islands being at least formed over said shallow heavily-doped drain diffusion regions formed within said common-drain diffusion regions between the pair of second sidewall dielectric spacers;
each of the pair of self-aligned split-gate regions comprises a single-side dish-shaped floating-gate structure being alternately formed on a first gate-dielectric layer in said active region with a first intergate-dielectric layer being formed on its top and a second intergate-dielectric layer being formed over its inner sidewall and tip portion; and
an elongated planarized control/select-gate conductive layer acted as a word line being formed over a surface alternately formed by a second gate-dielectric layer and said first/second intergate-dielectric layers in said active region and said first/second raised field-oxide layers in said parallel STI region; and
a plurality of first interconnect-metal layer integrated with the plurality of planarized common-drain conductive islands being simultaneously patterned and etched to form a plurality of bit lines transversely to the plurality of common-source conductive bus lines by using a plurality of hard masking layers, wherein each of the plurality of hard masking layers comprises a masking dielectric layer being aligned above said active region and two sidewall dielectric spacers being formed over each sidewall of said masking dielectric layer. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13)
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14. A contactless parallel common-source/drain conductive bit-lines flash memory array, comprising:
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a semiconductor substrate of a first conductivity type having a plurality of active regions and a plurality of parallel STI regions formed alternately, wherein each of the plurality of parallel STI regions is filled with a first raised field-oxide layer;
a plurality of common-source regions and a plurality of virtual-gate regions being formed alternately and transversely to the plurality of parallel STI regions, wherein each of the plurality of virtual-gate regions includes a pair of self-aligned split-gate regions being located in each side portion and a common-drain region being located between the pair of self-aligned split-gate regions;
each of the plurality of common-source regions comprises a pair of first sidewall dielectric spacers being formed over each sidewall of nearby said virtual-gate regions and on a portion of a first flat bed being alternately formed by an etched first raised field-oxide layer in said parallel STI region and a shallow heavily-doped source diffusion region formed within a common-source diffusion region of a second conductivity type in said active region;
a common-source conductive bus line being formed over said first flat bed between the pair of first sidewall dielectric spacers; and
a first planarized thick-oxide layer being formed over said common-source conductive bus line;
said common-drain region comprises a pair of second sidewall dielectric spacers being formed over each sidewall of nearby said self-aligned split-gate regions and on a portion of a second flat bed being alternately formed by an etched second raised field-oxide layer in said parallel STI region and a shallow heavily-doped drain diffusion region formed within a common-drain diffusion region of said second conductivity type in said active region;
a common-drain conductive bus line being formed over said second flat bed between the pair of second sidewall dielectric spacers; and
a second planarized thick-oxide layer being formed over said common-drain conductive bus line;
each of the pair of self-aligned split-gate regions comprises a single-side dish-shaped floating-gate structure being alternately formed on a first gate-dielectric layer in each of said active regions with a first intergate-dielectric layer being formed on its top and a second intergate-dielectric layer being formed over its inner sidewall and tip portion; and
a planarized control/select-gate conductive island being at least formed alternately over a second gate-dielectric layer and the first/second intergate-dielectric layers in said active region and a portion of said first/second raised field-oxide layers in said parallel STI region; and
a plurality of first interconnect-metal layers integrated with the plurality of planarized control/select-gate conductive islands being simultaneously patterned and etched to form a plurality of word lines transversely to the plurality of common-source/drain conductive bus lines by using a plurality of hard masking layers, wherein each of the plurality of hard masking layers comprises a masking dielectric layer being aligned above said active region and two sidewall dielectric spacers being formed over each sidewall of said masking dielectric layer. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification