Power semiconductor device having trench gate structure and method for manufacturing the same

• US 6,525,373 B1
• Filed: 06/28/1999
• Issued: 02/25/2003
• Est. Priority Date: 06/30/1998
• Status: Expired due to Fees

• Current Assignee: Fairchild Korea Semiconductor Limited (ON Semiconductor Corporation)
• Original Assignee: Fairchild Korea Semiconductor Limited (ON Semiconductor Corporation)
• Inventors: Kim, Han-soo
• Primary Examiner(s): Loke, Steven
• Assistant Examiner(s): Kang, Donghee
• Application Number:
  US09/340,382
• Time in Patent Office: 1,338 Days
• Field of Search: 257/330-332, 257/350, 257/333, 257/334, 257/328, 257/329, 257/407, 257/410, 257/411, 257/412, 257/413, 438/270-271, 438/259, 438/589
• US Class Current: 257/330
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power semiconductor device having a trench gate structure in which it is possible to reduce the number of required masks and to improve its characteristics, and a method for manufacturing the same, includes a semiconductor substrate and a semiconductor region of a first conductive type formed on the semiconductor substrate. A source region of a second conductive type is formed on the semiconductor region. A trench is formed to pass through the source region and the semiconductor region of the first conductive layer. A first conductive layer formed to be insulated from the semiconductor substrate by interposing a gate insulating film, and a gate formed of a second conductive layer surrounded by the first conductive layer are formed in the trench. An interlayer dielectric film is formed on the semiconductor substrate. A gate electrode is formed connected to the gate through a contact hole formed in the interlayer dielectric film. A source electrode is formed connected to the source region through a second contact hole formed in the interlayer dielectric film.

Claims

1. A power semiconductor device of a trench gate structure, comprising:

a semiconductor substrate;

a semiconductor region of a first conductive type formed on the semiconductor substrate;

a source region of a second conductive type formed on the semiconductor region;

a gate formed in a trench formed to pass through the source region and the semiconductor region, said gate formed of a first conductive polysilicon layer formed to be insulated from the semiconductor substrate by interposing a gate insulating film, and formed of a second conductive metal layer surrounded by the first conductive polysilicon layer, wherein both the first conductive polysilicon layer and the second conductive metal layer extend to a depth which passes through the source region and the semiconductor region to the semiconductor substrate;

an interlayer dielectric film formed on the semiconductor substrate;

a gate electrode connected to the gate through a first contact hole formed in the interlayer dielectric film; and

a source electrode connected to the source region through a second contact hole formed in the interlayer dielectric film.

2. The power semiconductor device of claim 1, where in a width of the upper surface of the gate is equal to or less than a width of a trench.

3. The power semiconductor device of claim 1, wherein the trench is circular in a plane parallel to a top surface of said semiconductor substrate.

4. The power semiconductor device of claim 1, wherein the trench has a shape of a polygon having at least five sides in a plane parallel to a top surface of said semiconductor substrate.

5. The power semiconductor device of claim 1, wherein the width of the trench in the part in which the gate contacts a gate electrode is 2 μ

m.

6. The power semiconductor device of claim 1, wherein the semiconductor substrate comprises:

a first region highly doped with second conductive type impurities; and

a second conductive region formed on the first region and doped with the second conductive type impurities of low concentration.

7. The power semiconductor device of claim 1, wherein the semiconductor substrate comprises:

a first region highly doped with first conductive type impurities;

a second region highly doped with second conductive type impurities; and

a third region formed on the first region and doped with the second conductive type impurities of low concentration.

8. A power semiconductor device of a trench gate structure, comprising:

a semiconductor substrate;

a semiconductor region of a first conductive type formed on the semiconductor substrate;

a source region of a second conductive type formed on the semiconductor region;

a trench having inner walls defining an opening in the source region and extending through the semiconductor region to the semiconductor substrate;

a gate insulating film covering the inner walls of the trench;

a gate comprising a first conductive layer and a second conductive layer, the first conductive layer covering the gate insulating film within the trench, and the second conductive layer surrounded by the first conductive layer and extending through a center of the trench from the opening of the trench;

a dielectric layer located over the source region and the trench, the dielectric layer having first and second openings defined therein, wherein the first opening is aligned over the second conductive layer of the gate, and wherein the first opening has a width which is greater than a width of the second conductive layer and less than a width of the trench;

a gate electrode extending through the first opening in the dielectric layer and contacting the gate; and

a source electrode extending through the second opening in the dielectric layer and contacting the source region.

9. The power semiconductor device of claim 8, wherein the first conductive layer is polysilicon, and the second conductive layer is metal.