Semiconductor device having trench filled up with gate electrode

• US 6,525,375 B1
• Filed: 10/16/2000
• Issued: 02/25/2003
• Est. Priority Date: 10/19/1999
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Shibata, Takumi, Yamaguchi, Hitoshi, Sakakibara, Jun, Morishita, Toshiyuki, Sakakibara, Toshio
• Primary Examiner(s): Tran, Minh Loan
• Assistant Examiner(s): Dickey, Thomas L
• Application Number:
  US09/688,154
• Time in Patent Office: 862 Days
• Field of Search: 257/329, 257/330, 257/335, 257/336, 257/341, 257/342, 257/344, 257/327, 257/378, 257/401, 257/491-493
• US Class Current: 257/341
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66378 the other device being a controlling field-effect device
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66787 with a gate at the side of the channel
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/749 with turn-on by field effect
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 : Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7817 : structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7824 : with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/7825 : with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 : without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/7835 : with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

In a semiconductor device, a p-type base region is provided in an n⁻-type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n⁺-type source region extends in the p-type base region from the principal surface in the perpendicular direction, and an n⁺-type drain region extends in the substrate separately from the p-type base region with a drift region interposed therebetween. A trench is formed to penetrate the p-type base region from the n⁺-type source region in a direction parallel to the principal surface. A gate electrode is formed in the trench through a gate insulating film. Accordingly, a channel region can be formed with a channel width in a depth direction of the trench when a voltage is applied to the gate electrode.

Claims

1. A semiconductor device comprising:

a semiconductor substrate that comprises a principal surface and a back surface opposite to the principal surface, wherein the semiconductor substrate further comprises a first semiconductor region on a side of the principal surface, a second semiconductor region that vertically and laterally encompasses the first semiconductor region and a third semiconductor region that vertically and laterally encompasses the second semiconductor region;

a trench disposed on the side of the principal surface, wherein the trench has a contour that laterally traverses from the first semiconductor region through the second semiconductor region and into the third semiconductor region;

a gate electrode for filling the trench;

a MOS structure formed on a sidewall of the trench, wherein the MOS structure has a channel width defined along a depth direction of the semiconductor substrate; and

a lateral impurity concentration profile within the second semiconductor region, wherein the lateral impurity concentration profile has a uniform concentration along the depth direction of the semiconductor substrate.

2. A semiconductor device according to claim 1, wherein the trench penetrates the second semiconductor region vertically to the third semiconductor region.

3. A semiconductor device according to claim 1, wherein the semiconductor substrate further comprises a fourth semiconductor region disposed on a side of the back surface.

4. A semiconductor device according to claim 3, wherein an electrical conduction is created between the first semiconductor region and the fourth semiconductor region and through the second semiconductor region and the third semiconductor region.

5. A semiconductor device according to claim 4, wherein the fourth semiconductor region laterally and vertically encompasses the third semiconductor region.

6. A semiconductor device according to claim 5, wherein:

the first semiconductor region is heavily doped with impurities of n-type conductivity;

the second semiconductor region is moderately doped with impurities of p-type conductivity;

the third semiconductor region is lightly doped with impurities of n-type conductivity; and

the fourth semiconductor region is heavily doped with impurities of n-type conductivity.

7. A semiconductor device according to claim 6, wherein:

the first semiconductor region defines a source region;

the second semiconductor region defines a base region;

the third semiconductor region defines a drift region; and

the fourth semiconductor region defines a drain region.

8. A semiconductor device comprising:

a semiconductor substrate that comprises a principal surface and a back surface opposite to the principal surface, wherein the semiconductor substrate further comprises a first semiconductor region on a side of the principal surface, a second semiconductor region that vertically and laterally encompasses the first semiconductor region and a third semiconductor region that vertically and laterally encompasses the second semiconductor region;

a trench disposed on the side of the principal surface, wherein the trench has a contour that laterally traverses from the first semiconductor region through the second semiconductor region and into the third semiconductor region;

a gate electrode for filling the trench;

a MOS structure formed on a sidewall of the trench, wherein the MOS structure has a channel width defined along a depth direction of the semiconductor substrate; and

wherein the second semiconductor region is an epitaxial layer.

9. A semiconductor device according to claim 8, wherein the trench penetrates the second semiconductor region vertically to the third semiconductor region.

10. A semiconductor device according to claim 8, wherein the semiconductor substrate further comprises a fourth semiconductor region disposed on a side of the back surface.

11. A semiconductor device according to claim 10, wherein an electrical conduction is created between the first semiconductor region and the fourth semiconductor region and through the second semiconductor region and the third semiconductor region.

12. A semiconductor device according to claim 11, wherein the fourth semiconductor region laterally and vertically encompasses the third semiconductor region.

13. A semiconductor device according to claim 12, wherein:

the first semiconductor region is heavily doped with impurities of n-type conductivity;

the second semiconductor region is moderately doped with impurities of p-type conductivity;

the third semiconductor region is lightly doped with impurities of n-type conductivity; and

the fourth semiconductor region is heavily doped with impurities of n-type conductivity.

14. A semiconductor device according to claim 13, wherein:

the first semiconductor region defines a source region;

the second semiconductor region defines a base region;

the third semiconductor region defines a drift region; and

the fourth semiconductor region defines a drain region.

15. A semiconductor device comprising:

a semiconductor substrate that comprises a principal surface and a back surface opposite to the principal surface, wherein the semiconductor substrate further comprises a source region on a side of the principal surface, a base region that vertically and laterally encompasses the source region, a drift region that vertically and laterally encompasses the base semiconductor region and a drain region disposed on a side of the back surface;

a trench disposed on the side of the principal surface, wherein the trench has a contour that laterally traverses from the source region through the base region and into the drift semiconductor region;

a gate electrode for filling the trench; and

a MOS structure formed on a sidewall of the trench, wherein the MOS structure has a channel width defined along a depth direction of the semiconductor substrate.

16. A semiconductor device according to claim 15, wherein a relatively uniform potential difference between the source region and the drain region is maintained from the principal surface of the substrate to the back surface of the substrate.

17. A semiconductor device comprising:

a semiconductor substrate having a principal surface and a back surface being an opposite surface of the principal surface;

a base region of a first conductivity type provided in the semiconductor substrate and extending from the principal surface in a first direction perpendicular to the principal surface;

a source region of a second conductivity type provided in the base region and extending from the principal surface in the first direction;

a drift region provided in the semiconductor substrate at an opposite side of the base region with respect to the source region;

a drain region of the second conductivity type provided in the semiconductor substrate at a location remote from the base region;

a trench dug from the principal surface and penetrating the base region from the source region, in a second direction parallel to the principal surface;

a gate insulating film provided on a surface of the trench;

a gate electrode filling the trench through the gate insulating film;

a source electrode electrically connected to the source region and the base region; and

a drain electrode electrically connected to the drain region,

wherein the drift region, the base region and the source region respectively have impurity concentrations, each of which is substantially uniform in the first direction.

18. The semiconductor device according to claim 17, wherein the drain region extends in the semiconductor substrate from the principal surface in the first direction.

19. The semiconductor device according to claim 18, wherein the drain region has an impurity concentration that is uniform in the first direction.

20. The semiconductor device according to claim 18, further comprising:

a support substrate bonded to the back surface of the semiconductor substrate; and

an insulating film interposed between the support substrate and the semiconductor substrate,

wherein the support substrate, the insulating film, and the semiconductor substrate constitute an SOI substrate.

21. The semiconductor device according to claim 20, wherein the trench extends in the first direction and reaches the insulating film.

22. The semiconductor device according to claim 18, wherein the source region, the base region, the drift region and the drain region are arrayed in the second direction in succession.

23. The semiconductor device according to claim 18, wherein the trench extends from the principal surface in the first direction, penetrates the base region, and reaches the drain region.

24. The semiconductor device according to claim 18, wherein the source electrode and the drain electrode are disposed above the principal surface of the semiconductor substrate.

25. The semiconductor device according to claim 18, further comprising a resistance lowering layer provided in one of the drain region and the source region and extending from the principal surface in the first direction, the resistance lowering layer having a resistivity lower than that of the one of the drain region and the source region.

26. The semiconductor device according to claim 17, wherein the drain region has a first drain part extending from the principal surface of the semiconductor substrate in the first direction, and a second drain part integrated with the first drain part and provided at a side of the back surface of the semiconductor substrate.

27. The semiconductor device according to claim 26, wherein:

the source electrode is provided above the principal surface of the semiconductor substrate and electrically connected to the source region and the base region; and

the drain electrode is provided above the back surface of the semiconductor substrate and electrically connected with the drain region.

28. The semiconductor device according to claim 17, wherein the drain region is provided at a side of the back surface of the semiconductor substrate.

29. The semiconductor device according to claim 17, wherein:

the trench includes first and second trenches that are arranged in the semiconductor substrate in a third direction parallel to the principal surface and perpendicular to the second direction; and

the base region is disposed between the first and second trenches and electrically connected with the source electrode.

30. The semiconductor device according to claim 29, wherein:

the base region is provided at both sides of the source region; and

each of the first and second trenches is divided into two parts at a center of the source region.

31. The semiconductor device according to claim 29, wherein:

the base region, the drift region, and the drain region are concentrically disposed about the source region being a center; and

the trench includes a plurality of trenches disposed radially about the source region.

32. The semiconductor device according to claim 29, wherein:

the drift region, the base region and the source region are disposed concentrically about the drain region being a center; and

the trench includes a plurality of trenches disposed radially about the drain region.

33. The semiconductor device according to claim 29, further comprising a gate wiring member connected to the gate electrode, the gate wiring member being connected to the gate electrode an end portion of the trench at a side of the drift region, and provided above a pn junction part provided between the drift region and the base region.

34. The semiconductor device according to claim 17, wherein:

the drain region extends from the principal surface of the semiconductor substrate in the first direction; and

an impurity diffusion layer of the first conductivity type is provided in the drain region and terminated at the principal surface of the semiconductor substrate.

35. The semiconductor device according to claim 17, wherein:

the source region are provided at only a first side of the trench;

the base region has a first part provided at the first side of the trench and a second part provided at a second side of the trench opposite the first side, the second part being an injection layer and electrically fixed to have a predetermined potential difference with respect to the drain region.

36. The semiconductor device according to claim 35, wherein:

the trench includes a plurality of trenches arranged in a third direction that is parallel to the principal surface and perpendicular to the second direction; and

at least one of the plurality of trenches has the injection layer at the second side thereof.

37. The semiconductor device according to claim 17, further comprising an injection layer of the first conductivity type provided in the drift region at a location remote from the base region and avoiding a region that is to be a channel region.

38. The semiconductor device according to claim 37, wherein the injection layer is provided in contact with a distal end portion of the trench that penetrates the base region from the source region and reaches the drift region.

39. The semiconductor device according to claim 17, further comprising an injection layer of the first conductivity type extending in the semiconductor substrate from the principal surface in the first direction at an opposite side of the drift region with respect to the base region.

40. The semiconductor device according to claim 17, further comprising an injection layer of the first conductivity type provided at a side of the back surface in the semiconductor substrate.

41. The semiconductor device according to claim 17, further comprising an injection layer of the first conductivity type provided in the semiconductor substrate and electrically connected to the gate electrode.

42. The semiconductor device according to claim 41, wherein the injection layer is electrically connected to the gate electrode through a resistor.

43. The semiconductor device according to claim 17, further comprising a contact layer provided in the base region and extending from the principal surface of the semiconductor substrate in the first direction.

44. The semiconductor device according to claim 17, wherein a depth of the trench in the first direction is in a range of 5 μ

m to 300 μ

m.

45. The semiconductor device according to claim 44, wherein the depth of the trench is in a range of 20 μ

m to 100 μ

m.

46. The semiconductor device according to claim 17, wherein the trench extends in the semiconductor substrate in the first direction and is terminated in one of the base region and the source region.

47. The semiconductor device according to claim 17, wherein:

when a voltage is applied to the gate electrode, a channel region is formed in a portion of the base region adjoining the trench, the channel region having a width in the first direction and allowing a current to flow therein in the second direction.

48. The semiconductor device according to claim 17, wherein each of the impurity concentrations of the source region, the base region and the drain region further is substantially uniform in the second direction except in junction vicinities.

49. A semiconductor device comprising:

a semiconductor substrate having a principal surface and a back surface being an opposite surface of the principal surface;

a base region of a first conductivity type provided in the semiconductor substrate and extending from the principal surface in a first direction perpendicular to the principal surface;

a source region of a second conductivity type provided in the base region and extending from the principal surface in the first direction;

a drift region provided in the semiconductor substrate at an opposite side of the base region with respect to the source region;

a drain region of the second conductivity type provided in the semiconductor substrate at a location remote from the base region;

a trench dug from the principal surface, extending in the first direction, and penetrating the base region from the source region in a second direction;

a gate insulating film provided on a surface of the trench;

a gate electrode filling the trench through the gate insulating film;

a source electrode electrically connected to the source region and the base region; and

a drain electrode electrically connected to the drain region,

wherein the drift region, the base region and the source region respectively have impurity concentrations, each of which is substantially uniform in the first direction.

50. The semiconductor device according to claim 49, wherein:

the drain region extends from the principal surface of the semiconductor substrate in the first direction; and

the drain region has an impurity concentration that is uniform in the first direction.

51. The semiconductor device according to claim 49, wherein, when a voltage is applied to the gate electrode, a channel region is formed in a portion of the base region adjoining the trench, the channel region having a width in the first direction and allowing a current to flow therein in the second direction.

52. The semiconductor device according to claim 49, wherein the drain region is provided at a side of the back surface of the semiconductor substrate.

57. The semiconductor device according to claim 49, wherein each of the impurity concentrations of the source region, the base region and the drain region further is substantially uniform in the second direction except in junction vicinities.

53. A semiconductor device comprising:

a semiconductor substrate having a principal surface and a back surface being an opposite surface of the principal surface;

a base region of a first conductivity type provided in the semiconductor substrate and extending from the principal surface in a first direction perpendicular to the principal surface;

a source region of a second conductivity type provided in the base region and extending from the principal surface in the first direction;

a drift region provided in the semiconductor substrate at an opposite side of the base region with respect to the source region;

a drain region of the second conductivity type provided in the semiconductor substrate at a location remote from the base region;

a trench dug from the principal surface and penetrating the base region from the source region in a second direction parallel to the principal surface;

a gate insulating film provided on a surface of the trench;

a gate electrode filling the trench through the gate insulating film;

a source electrode electrically connected to the source region and the base region;

a drain electrode electrically connected to the drain region; and

a channel region formed in a portion of the base region adjoining the trench so that a current flows in the channel region in the second direction when a voltage is applied to the gate electrode, the channel region having a width in the first direction that corresponds to a depth direction of the trench.

54. The semiconductor device according to claim 53, wherein the drain region has a first drain part extending from the principal surface in the first direction and a second drain part integrated with the first drain part and extending in the second direction at a side of the back surface.

55. The semiconductor device according to claim 53, wherein the drift region, the base region, the source region, and the drain region respectively have impurity concentrations, each of which is uniform in the first direction.

56. The semiconductor device according to claim 55, wherein each of the impurity concentrations of the source region, the base region and the drain region further is substantially uniform in the second direction except in junction vicinities.

58. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type, having a principal surface and a back surface at an opposite side of the principal surface;

a source region of a second conductivity type provided in the semiconductor substrate and extending from the principal surface in a first direction perpendicular to the principal surface;

a drain region of the second conductivity type provided in the semiconductor substrate at a location remote from the source region;

a trench dug from the principal surface and extending from the source region to the drain region in a second direction;

a gate insulating film provided on a surface of the trench;

a gate electrode filling the trench through the gate insulating film;

a source electrode electrically connected to the source region; and

a drain electrode electrically connected to the drain region,

wherein the source region, the base region and the drain region respectively have impurity concentrations, each of which is substantially uniform in the first direction; and

wherein, when a voltage is applied to the gate electrode, a channel region is formed in a portion of the semiconductor substrate adjoining the trench, the channel region having a channel width in a depth direction of the trench so as to allow a current to flow therein in a direction parallel to the principal surface.

61. The semiconductor device according to claim 58, wherein each of the impurity concentrations of the source region, the base region and the drain region further is substantially uniform in the second direction except in junction vicinities.

59. A semiconductor device comprising:

a semiconductor substrate having a principal surface and a back surface being an opposite surface of the principal surface;

a first conductivity type base region extending in the semiconductor substrate from the principal surface in a first direction perpendicular to the principal surface;

a second conductivity type source region extending in the base region from the principal surface in the first direction;

a drift region provided at an opposite side of the base region with respect to the source region;

a second conductivity type drain region extending in the semiconductor substrate from the principal surface in the first direction separately from the base region;

a trench dug from the principal surface and penetrating the base region from the source region in a second direction parallel to the principal surface;

a gate insulating film provided on a surface of the trench;

a gate electrode provided on a surface of the gate insulating film;

a source electrode electrically connected to the source region and the base region;

a drain electrode electrically connected to the drain region,

wherein the drift region, the base region, the source region, and the drain region respectively have impurity concentrations, each of which is substantially uniform in a depth direction of the semiconductor substrate.

60. A semiconductor device comprising:

a semiconductor substrate having a principal surface and a back surface being an opposite surface of the principal surface;

a first conductivity type base region extending in the semiconductor substrate from the principal surface in a first direction perpendicular to the principal surface;

a second conductivity type source region extending in the base region from the principal surface in the first direction;

a drift region provided at an opposite side of the base region with respect to the source region;

a second conductivity type drain region extending in the semiconductor substrate from the principal surface in the first direction separately from the base region;

a trench dug from the principal surface, extending in the semiconductor substrate in the first direction, and penetrating the base region from the source region in a second direction;

a gate insulating film provided on a surface of the trench;

a gate electrode provided on a surface of the gate insulating film;

a source electrode electrically connected to the source region and the base region; and

a drain electrode electrically connected to the drain region,

wherein the drift region, the base region, the source region, and the drain region respectively have impurity concentrations, each of which is uniform in a depth direction of the semiconductor substrate.