Semiconductor device having chip scale package

• US 6,525,412 B2
• Filed: 11/30/2001
• Issued: 02/25/2003
• Est. Priority Date: 11/30/2000
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Noshita, Kazuyuki
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, MAI HUONG C
• Application Number:
  US10/007,165
• Publication Number:
  US 20020063264A1
• Time in Patent Office: 452 Days
• Field of Search: 257/668, 257/680, 257/779, 257/780, 257/784, 324/755
• US Class Current: 257/678
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/4943 the connecting portions being staggered
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/92147 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/50 Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto thin flexible metallic tape with or without a film carrier H01L23/49572, flexible insulating substrates H01L23/4985, H01L23/5387
• CPC Class Codes: H01L 24/86 using tape automated bonding [TAB]
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18165 : of a wire bonded chip

Abstract

A first surface of a semiconductor chip and an upper surface of a circuit board are bonded with a pad of the semiconductor chip fitted to a first opening of the circuit board. The pad is electrically connected to a wire of the circuit board. The pad is sealed with a first resin. A second resin is disposed on the upper surface of the circuit board. A second resin includes an upper surface at a height substantially equal to a height of a second surface of the semiconductor chip at a point apart from a corner of a square of the first surface of the semiconductor chip.

Claims

1. A semiconductor device comprising:

a semiconductor chip including a pad disposed on a square first surface;

a circuit board including upper surface contacting the first surface of said semiconductor chip, including a first opening arranged below the pad, and including a wire arranged on a lower surface and electrically connected to the pad;

a first resin arranged on the first opening and coating the pad; and

a second resin disposed on the upper surface of said circuit board, and including an upper surface at a height substantially equal to a height of a second surface of said semiconductor chip at a point apart from a corner of the square first surface of said semiconductor chip.

2. The semiconductor device as claimed in claim 1, wherein a second opening is provided on said circuit board in a vicinity of the corner of the square first surface of said semiconductor chip, and said second resin is provided in said second opening.

3. The semiconductor device as claimed in claim 2, wherein the corner of the square first surface of said semiconductor chip is arranged over said second opening.

4. The semiconductor device as claimed in claim 2, wherein the pad is provided in a vicinity of a side of the square first surface, and the first opening serves as the second opening.

5. The semiconductor device as claimed in claim 2, wherein a shape of an opening face of the second opening is a circle, a square or a polygon.

6. The semiconductor device as claimed in claim 2, wherein the second opening has a plurality of openings.

7. The semiconductor device as claimed in claim 1, wherein the upper surface of said second resin and the second surface of said semiconductor chip are arranged on a plane.

8. The semiconductor device as claimed in claim 1, wherein said second resin contacts with a periphery of the second surface of said semiconductor chip.

9. The semiconductor device as claimed in claim 1, wherein a side of the square first surface of said semiconductor chip is arranged over said first opening.

10. The semiconductor device as claimed in claim 1, wherein the pad is arranged in the vicinity of a centerline perpendicular to a side of the square first surface.

11. The semiconductor device as claimed in claim 1, wherein a third opening is provided on said circuit board in the vicinity of a side of the square first surface, a third resin is provided in the third opening, and the third resin is arranged on a side face of said semiconductor chip.

12. The semiconductor device as claimed in claim 11, wherein a shape of an opening face of the third opening is a circle, a square or a polygon.

13. The semiconductor device as claimed in claim 11, wherein the third opening has a plurality of openings.

14. The semiconductor device as claimed in claim 1, wherein said semiconductor device including a bump arranged below the wire and electrically connected to the wire.

15. The semiconductor device as claimed in claim 1, wherein the pad is electrically connected to the wire by a wire.