Wafer-level burn-in and test

• US 6,525,555 B1
• Filed: 05/16/2000
• Issued: 02/25/2003
• Est. Priority Date: 11/16/1993
• Status: Expired due to Fees

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Khandros, Igor Y., Pedersen, David V.
• Primary Examiner(s): Sherry, Michael
• Assistant Examiner(s): HOLLINGTON, JERMELE M
• Application Number:
  US09/573,489
• Time in Patent Office: 1,015 Days
• Field of Search: 324/765, 324/754, 324/755, 324/760, 324/761
• US Class Current: 324/750.07
• CPC Class Codes: G01R 31/287 Procedures; Software aspects
• CPC Class Codes: G01R 31/2874 related to temperature
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]

Abstract

Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate having active electronic components such as ASICs mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. The spring contact elements may be mounted to either the DUTs or to the ASICs, and may fan out to relax tolerance constraints on aligning and interconnecting the ASICs and the DUTs. Physical alignment techniques are also described.

Claims

1. A method comprising:

providing a semiconductor wafer comprising unsingulated dice, each of said die comprising a plurality of pads;

permanently attaching a plurality of resilient conductive contact elements to said pads;

providing a test substrate comprising;

a plurality of wafer contacts, and

active electronics;

bringing ones of said wafer contacts into electrical contact with ones of said resilient, conductive contact elements;

receiving at said test substrate test data from a semiconductor tester;

said active electronics processing said test data; and

exercising at least a portion of said wafer in accordance with said processed test data.

2. The method of claim 1, wherein said processing comprises converting at least a portion of said test data from a first format to a second format.

3. The method of claim 1, wherein said test data comprises test commands, and said processing comprises generating test vectors for exercising said at least a portion of said wafer.

4. The method of claim 1, wherein said active electronics regulates power supplied to said wafer.

5. The method of claim 1, wherein said permanently attaching a plurality of resilient conductive contact elements to said pads comprises lithographically forming said contact elements on said pads.

6. The method of claim 1, wherein said permanently attaching a plurality of resilient conductive contact elements to said pads comprises forming said contact elements and subsequently mounting said formed contact elements on said pads.

7. The method of claim 1, wherein said wafer contacts are disposed on said active electronics.

8. The method of claim 1, wherein said test substrate comprises a semiconductor material on which said active electronics have been fabricated.

9. The method of claim 1, wherein said test substrate has a coefficient of thermal expansion that is approximately equal to a coefficient of thermal expansion of said unsingulated semiconductor wafer comprising dice.

10. The method of claim 1 further comprising singulating said wafer after exercising at least a portion of said wafer.

11. The method of claim 1, wherein said permanently attaching a plurality of resilient conductive contact elements to said pads comprises wire bonding a wire to said pads.

12. The method of claim 11, wherein said permanently attaching a plurality of resilient conductive contact elements to said pads further comprises overcoating said wire.

13. The method of claim 1, wherein said exercising at least a portion of said wafer comprises testing at least one of said die, and said active electronics monitors results of said testing of said at least one die.

14. The method of claim 13, wherein said active electronics stops testing of any of said at least one die that fails a portion of said testing.

15. The method of claim 14, wherein said active electronics continues testing any of said at least one die that passes said portion of said testing.

16. The method of claim 1, wherein each of said plurality of resilient conductive contact elements comprises a base portion permanently attached to said pads and a contact portion displaced from said wafer.

17. The method of claim 16, wherein a pitch of said base portions is different than a pitch of said contact portions.

18. The method of claim 17, wherein said pitch of said base portions is finer than said pitch of said contact portions.

19. The method of claim 1, wherein said bringing ones of said wafer contacts into electrical contact with ones of said resilient, conductive contact elements comprises bringing said contact elements into contact with capture features on said wafer contacts.

20. The method of claim 19, wherein said capture features comprise indentations in said wafer contacts.

21. The method of claim 20, wherein said indentations comprise sloped side walls.

22. The method of claim 1, wherein said exercising at least a portion of said wafer comprises burning in said at least a portion of said wafer.

23. The method of claim 22, said burning in said at least a portion of said wafer comprises testing said at least a portion of said wafer.

24. The method of claim 22, wherein said burning in said at least a portion of said wafer comprises heating said wafer to a particular temperature.

25. The method of claim 24, wherein said particular temperature is at least 150 degrees centigrade.

26. The method of claim 24, wherein said active electronics is kept at a temperature that is less than said particular temperature of said wafer.

27. An apparatus comprising:

a semiconductor wafer comprising unsingulated dice, each of said die comprising a plurality of pads;

a plurality of resilient conductive contact elements permanently attached to said pads;

a semiconductor tester configured to generate data controlling exercise of said dice of said wafer; and

a test substrate in communication with said semiconductor tester, said test substrate comprising;

a plurality of wafer contacts, ones of said wafer contacts pressed against ones of said resilient, conductive contact elements, and

active electronics configured to process data received from said semiconductor tester.

28. The apparatus of claim 27, wherein said data received from said semiconductor tester comprises test commands, and said active electronics are configured to generate test vectors for exercising at least a portion of said wafer in response to said test commands.

29. The apparatus of claim 27, wherein said active electronics comprise a voltage regulator.

30. The apparatus of claim 27, wherein each of said plurality of resilient conductive contact elements comprises a lithographically formed contact element.

31. The apparatus of claim 27, wherein said wafer contacts are disposed on said active electronics.

32. The apparatus of claim 27, further comprising a heater configured to heat said wafer to a particular temperature.

33. The apparatus of claim 27 further comprising a vacuum chamber housing said wafer.

34. The apparatus of claim 27, wherein said test substrate further comprises a semiconductor material on which said active electronics have been fabricated.

35. The apparatus of claim 27, wherein said test substrate has a coefficient of thermal expansion that is approximately equal to a coefficient of thermal expansion of said unsingulated semiconductor wafer comprising said dice.

36. The apparatus of claim 27, wherein said data received from said semiconductor tester causes testing of said dice of said wafer, wherein said active electronics monitor results of said testing of said dice.

37. The apparatus of claim 36, wherein said active electronics are configured to stop testing of any of said dice that fail a portion of said testing.

38. The apparatus of claim 27, wherein each of said plurality of resilient conductive contact elements comprises a wire bonded to a pad.

39. The apparatus of claim 38, wherein each of said plurality of resilient conductive contact elements further comprises a coating over said wire.

40. The apparatus of claim 27, wherein each of said plurality of resilient conductive contact elements comprises a base portion permanently attached to a pad and a contact portion displaced from said wafer.

41. The apparatus of claim 40, wherein a pitch of said base portions is different than a pitch of said contact portions.

42. The apparatus of claim 41, wherein said pitch of said base portions is finer than said pitch of said contact portions.

43. The apparatus of claim 27, wherein said wafer contacts comprise capture features corresponding to said resilient conductive contact elements.

44. The apparatus of claim 43, wherein said capture features comprise indentations in said wafer contacts.

45. The apparatus of claim 44, wherein said indentations comprise sloped side walls.

46. An apparatus comprising:

a semiconductor wafer comprising unsingulated dice, each of said die comprising a plurality of pads,

a plurality of interconnection means each for providing resilient, pressure-based electrical connections to one of said pads, each of said interconnection means being permanently attached to one of said pads,

semiconductor tester means for generating data controlling exercise of said dice of said wafer; and

interface means for providing electrical connections between said semiconductor tester and said interconnection means,

said interface means comprising processing means for processing data relating to exercising said dice of said wafer.

47. The apparatus of claim 46, wherein said processing data relating to exercising said dice of said wafer comprises generating test vectors for exercising said dice.

48. The apparatus of claim 46, wherein said processing data relating to exercising said dice of said wafer comprises stopping testing of a failed die.

49. The apparatus of claim 46, wherein said processing data relating to exercising said dice of said wafer comprises regulating power supplied to said wafer.

50. The apparatus of claim 46, wherein said wafer contacts comprise capture means for receiving and aligning said resilient conductive contact elements.

51. The apparatus of claim 46, further comprising heating means for heating at least a portion of said wafer.

52. The apparatus of claim 51 further comprising insulating means for maintaining said processing means at a different temperature than said wafer.