Current-controlled CMOS circuits with inductive broadbanding

• US 6,525,571 B2
• Filed: 09/26/2001
• Issued: 02/25/2003
• Est. Priority Date: 02/24/2000
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Green, Michael M.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): CHO, JAMES HYONCHOL
• Application Number:
  US09/965,235
• Publication Number:
  US 20020017921A1
• Time in Patent Office: 517 Days
• Field of Search: 326/115, 326/83, 326/86-88, 326/112, 326/119, 326/121, 327/52, 327/50, 327/65, 327/81, 327/89, 330/253
• US Class Current: 326/115
• CPC Class Codes: H03F 1/42 Modifications of amplifiers to extend the bandwidth
• CPC Class Codes: H03F 2200/36 the amplifier comprising means for increasing the bandwidth
• CPC Class Codes: H03F 2203/45506 the CSC comprising only one switch
• CPC Class Codes: H03F 2203/45631 the LC comprising one or more capacitors, e.g. coupling capacitors
• CPC Class Codes: H03F 2203/45638 the LC comprising one or more coils
• CPC Class Codes: H03F 2203/45702 the LC comprising two resistors
• CPC Class Codes: H03F 2203/45704 the LC comprising one or more parallel resonance circuits
• CPC Class Codes: H03F 2203/7203 the gated amplifier being switched on or off by a switch in the bias circuit of the amplifier controlling a bias current in the amplifier
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03K 17/04163 in field-effect transistor switches
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 19/01707 in asynchronous circuits
• CPC Class Codes: H03K 19/09432 with coupled sources or source coupled logic H03K19/096 takes precedence

Abstract

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C³MOS) logic with inductive broadbanding fabricated in conventional CMOS process technology. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C³MOS logic with inductive broadbanding/C³MOS logic with low power conventional CMOS logic. The combined C³MOS logic with inductive broadbanding/C³MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Claims

1. A metal-oxide-semiconductor field-effect transistor (MOSFET) circuit fabricated on a silicon substrate, comprising:

first circuitry implemented using current-controlled complementary metal-oxide semiconductor (C³MOS) logic with inductive broadbanding wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, and wherein first and second series connected RL circuits respectively couple first and second output nodes of a logic element to a power supply node, the first circuitry being configured to operate at a first frequency; and

second circuitry implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, wherein the second circuitry is coupled to the first circuitry and is configured to operate at a second frequency that is lower than the first frequency.

2. The MOSFET circuit of claim 1 further comprising:

third circuitry implemented using current-controlled complementary metal-oxide semiconductor (C³MOS) logic without inductive broadbanding wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals,

wherein, the third circuitry is coupled between the first circuitry and the second circuitry, and is configured to operate at a third frequency that is lower than the first frequency but higher than the second frequency.

3. The MOSFET circuit of claim 2 wherein the MOSFET circuit comprises a high speed serializer,

wherein the second circuitry comprises a low frequency multiplexer configured to convert N signals into M signals having higher frequency than that of the N signals, where M is an integer that is smaller than N,

wherein the third circuitry comprises a mid frequency multiplexer configured to convert the M signals into P signals having higher frequency than that of the M signals, where P is an integer that is smaller than M, and

wherein the first circuitry comprises a high frequency multiplexer configured to convert the P signals into Q signals having higher frequency than that of the P signals, where Q is an integer that is smaller than P.

4. The MOSFET circuit of claim 3 wherein the high speed serializer further comprises a re-timing flip flop coupled to an output of the first circuitry and implemented using the C³MOS logic with inductive broadbanding.

5. The MOSFET circuit of claim 4 wherein the flip flop comprises:

a first clocked latch comprising;

first and second n-channel MOSFETs having their source terminals connected together, their gate terminals coupled to receive a pair of differential logic signals, respectively, and their drain terminals connected to a first output and a second output, respectively;

a first clocked n-channel MOSFET having a drain terminal coupled to the source terminals of the first and second n-channel MOSFETs, a gate terminal coupled to receive a first clock signal CK, and a source terminal;

third and fourth n-channel MOSFETs having their source terminals coupled together, their gate terminals and drain terminals respectively cross-coupled to the first output and the second output;

a second clocked n-channel MOSFET having a drain terminal coupled to the source terminals of the third and fourth n-channel MOSFETs, a gate terminal coupled to receive a second clock signal CKB, and a source terminal;

first and second RL series circuits respectively coupling the first output and the second output to a logic high level; and

a second clocked latch coupled to the first clocked latch and comprising;

fifth and sixth n-channel MOSFETs having their source terminals connected together, their gate terminals coupled to the first output and the second output, respectively, and their drain terminals connected to a third output and a fourth output, respectively;

a third clocked n-channel MOSFET having a drain terminal coupled to the source terminals of the fifth and sixth n-channel MOSFETs, a gate terminal coupled to receive the second clock signal CKB, and a source terminal;

seventh and eighth n-channel MOSFETs having their source terminals coupled together, their gate terminals and drain terminals respectively cross-coupled to the third output and the fourth output;

a fourth clocked n-channel MOSFET having a drain terminal coupled to the source terminals of the seventh and eighth n-channel MOSFETs, a gate terminal coupled to receive the first clock signal CK, and a source terminal;

third and fourth RL series circuits respectively coupling the third output and the fourth output to a logic high level;

wherein, the gate terminals of the fifth and sixth n-channel MOSFETs in the second clocked latch respectively couple to the first output and the second output of the first clocked latch.

6. The MOSFET circuit of claim 3 wherein the high frequency multiplexer comprises:

first and second n-channel MOSFETs having their source terminals coupled to a first node, their gate terminals coupled to receive a first pair of differential logic signals, respectively, and their drain terminals coupled to a true output and a complementary output, respectively;

third and fourth n-channel MOSFETs having their source terminals coupled to a second node, their gate terminals coupled to receive a second pair of differential logic signals, and their drain terminals coupled to the true output and the complementary output, respectively;

first and second RL series circuits respectively coupling the true output and the complementary output to a logic high level;

a first select n-channel MOSFET having a drain terminal coupled to the first node, a gate terminal coupled to receive a first select logic signal, and a source terminal; and

a second select n-channel MOSFET having a drain terminal coupled to the second node, a gate terminal coupled to receive a second select logic signal, and a source terminal.

7. The MOSFET circuit of claim 2 wherein the MOSFET circuit comprises a high speed deserializer,

wherein the first circuitry comprises a high frequency demultiplexer configured to convert N signals into M signals having lower frequency than that of the N signals, where M is an integer that is larger than N,

wherein the third circuitry comprises a mid frequency demultiplexer configured to convert the M signals into P signals having lower frequency than that of the M signals, where P is an integer that is smaller than M, and

wherein the second circuitry comprises a low frequency demultiplexer configured to convert the P signals into Q signals having lower frequency than that of the P signals, where Q is an integer that is smaller than P.

8. The MOSFET circuit of claim 2 wherein the circuit comprises a serializer/deserializer, the serializer/deserializer comprising:

a first deserializer implemented by the C³MOS logic with inductive broadbanding, and configured to receive an input signal having the first frequency and to generate N first signals having the third frequency, where N is a positive integer greater than one;

a second deserializer implemented by the C³MOS logic without inductive broadbanding, coupled to the first serializer and configured to receive the N first signals and to generate M second signals having the second frequency, where M is a positive integer that is greater than N;

core circuitry implemented by the CMOS logic, and coupled to the second deserializer, the core circuitry being configured to process the M second signals to generate M processed signals;

a first serializer implemented by the C³MOS logic without inductive broadbanding, and coupled to the core circuitry, the first serializer being configured to receive the M processed signals and to generate N second output signals having the third frequency; and

a second serializer implemented by the C³MOS with inductive broadbanding logic, and coupled to the first serializer, the second serializer being configured to receive the N second output signals and to generate an output signal having the first frequency.

9. The MOSFET circuit of claim 8 further comprising:

an input circuit having an input coupled to a fiber optic channel and an output;

a clock and data recovery circuit having an input coupled to the output of the input circuit, and an output coupled to an input of the serializer/deserializer; and

an output driver having an input coupled to an output of the serializer/deserializer, and an output coupled to the fiber optic channel.

10. The MOSFET circuit of claim 9 wherein the input circuit comprises:

a photo detect device coupled to receive an optical signal from the optic channel and to convert the optical signal to an electrical signal; and

a driver circuit coupled to the photo detect and configured to amplify and drive the electrical signal.

11. The MOSFET circuit of claim 10 wherein the output driver comprises a laser driver configured to drive an electrical signal from the output of the serializer/deserializer onto the fiber optic channel.