Method and apparatus for local and global power management in a programmable analog circuit

• US 6,525,593 B1
• Filed: 08/22/2001
• Issued: 02/25/2003
• Est. Priority Date: 10/26/2000
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Mar, Monte
• Primary Examiner(s): ZWEIZIG, JEFFERY SHAWN
• Application Number:
  US09/935,454
• Time in Patent Office: 552 Days
• Field of Search: 327/530, 327/534, 327/560, 327/561, 327/562, 327/563, 327/564, 327/565
• US Class Current: 327/530
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06G 7/06 Programming arrangements, e.g. plugboard for interconnecting functional units of the computer; Digital programming hybrid computers G06J
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 2203/45454 the CSC comprising biasing means controlled by the input signal
• CPC Class Codes: H03F 2203/45471 the CSC comprising one or more extra current sources
• CPC Class Codes: H03F 2203/45476 the CSC comprising a mirror circuit
• CPC Class Codes: H03F 2203/45504 the CSC comprising more than one switch
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/014 Modifications of generator to ensure starting of oscillations
• CPC Class Codes: H03K 3/02315 Stabilisation of output, e.g. using crystal

Abstract

A method and apparatus for local and global power management in a programmable analog circuit. Specifically, the present invention describes an array of programmable analog blocks. Each block contains current mirror circuits that are coupled in parallel fashion. The mirror circuits function to increase current consumption in a corresponding operational amplifier more current when enabled. Global power management is achieved by increasing and decreasing the bias voltage that is applied to the array. Global configuration bits select the bias voltage value, including electrically disabling the bias voltage from the array of programmable analog blocks. Local power management is provided by enabling or disabling mirror circuits with local configuration bits to adjust the performance in an operational amplifier contained within a corresponding programmable analog block. A microcontroller controls the local and global management of power through the programmable analog block.

Claims

1. A programmable analog circuit having global and local power management comprising:

a first programmable analog block having a first plurality of mirror circuits coupled in parallel for adjusting performance of said first programmable analog block, including a first mirror circuit;

a bias voltage for biasing said first programmable analog block;

a plurality of global configuration bits for increasing said bias voltage for adjusting performance of said first programmable analog block; and

a first plurality of local configuration bits for controlling said first plurality of mirror circuits for adjusting performance of said first programmable analog block.

2. The programmable analog circuit as described in claim 1, wherein said first programmable analog block includes a first operational amplifier.

3. The programmable analog circuit as described in claim 2, wherein said first plurality of mirror circuits is a first plurality of current mirrors coupled in parallel.

4. The programmable analog circuit as described in claim 3, further comprising:

a first combination of said first plurality of local configuration bits for increasing current through said first operational amplifier for adjusting performance of said first programmable analog block by selectively enabling current mirrors in said first plurality of current mirrors.

5. The programmable analog circuit as described in claim 3, further comprising:

a first combination of said first plurality of local configuration bits for decreasing current through said first operational amplifier for adjusting performance of said first programmable analog block by selectively disabling current mirrors in said first plurality of current mirrors, said first combination of said first plurality of local configuration bits including disabling all current mirrors in said first plurality of current mirrors to effectively shut down said first programmable analog block.

6. The programmable analog circuit as described in claim 3, wherein each successive current mirror in said plurality of first current mirrors provides an increase in current.

7. The programmable analog circuit as described in claim 3, further comprising:

a second programmable analog block coupled in parallel to said to said first programmable analog block;

a second operational amplifier contained within said second programmable analog block,

a second plurality of current mirrors contained within said second programmable analog block that are coupled in parallel for adjusting performance of said second programmable analog block, said bias voltage biasing said second programmable analog block, said plurality of global configuration bits for increasing said bias voltage for adjusting performance of said second programmable analog block; and

a second plurality of local configuration bits for controlling said second plurality of current mirrors, and for adjusting performance of said second programmable analog block.

8. The programmable analog circuit as described in claim 7 further comprising:

a second combination of said second plurality of local configuration bits for increasing current through said second operational amplifier for adjusting performance of said second programmable analog block by selectively enabling current mirrors in said second plurality of current mirrors.

9. The programmable analog circuit as described in claim 7, further comprising:

a second combination of said second plurality of local configuration bits for decreasing current through said second operational amplifier for adjusting performance of said second programmable analog block by selectively disabling current mirrors in said second plurality of current mirrors, said second combination of said second plurality of local configuration bits including disabling all current mirrors in said second plurality of current mirrors to effectively shut down said second programmable analog block.

10. A programmable analog circuit having global and local power management comprising:

an array of programmable analog blocks that are coupled in parallel, including a first programmable analog block and a second programmable analog block;

said first programmable analog block including a first plurality of mirror circuits that are coupled in parallel for adjusting performance of said first programmable analog block, said first programmable analog block including a first operational amplifier, said first programmable analog block controlled by a first plurality of local configuration bits for selectively cutting in and removing mirror circuits in said first plurality of mirror circuits;

said second programmable analog block including a second plurality of mirror circuits that are coupled in parallel for adjusting performance of said second programmable analog block, said second programmable analog block including a second operational amplifier, said second programmable analog block controlled by a second plurality of local configuration bits for selectively cutting in and removing mirror circuits in said second plurality of mirror circuits;

a bias voltage for biasing said array of programmable analog blocks; and

a plurality of global configuration bits for controlling said bias voltage for adjusting performance of said array of programmable analog blocks.

11. The programmable analog circuit as described in claim 10, wherein each of said first plurality of mirror circuits is a first plurality of current mirrors, and each of said second plurality of mirror circuits is a second plurality of current mirrors.

12. The programmable analog circuit as described in claim 10, further comprising a first combination of said plurality global configuration bits for increasing said bias voltage for adjusting performance of said array of programmable analog blocks.

13. The programmable analog circuit as described in claim 10, further comprising a second combination of said plurality of global configuration bits for decreasing said bias voltage for adjusting performance of said array of programmable analog blocks, said second combination of said plurality of global configuration bits including electrically disabling said array of programmable analog blocks.

14. The programmable analog circuit as described in claim 10, further comprising:

a first combination of said first plurality of local configuration bits for increasing current through said first operational amplifier for adjusting performance of said first programmable analog block by selectively enabling current mirrors in said first plurality of current mirrors; and

a second combination of said second plurality of local configuration bits for increasing current through said second operational amplifier for adjusting performance of said second programmable analog block by selectively enabling current mirrors in said second plurality of current mirrors.

15. The programmable analog circuit as described in claim 10, further comprising:

a first combination of said first plurality of local configuration bits for decreasing current through said first operational amplifier for adjusting performance of said first programmable analog block by selectively disabling current mirrors in said first plurality of current mirrors, said first combination of said first plurality of local configuration bits including disabling all current mirrors in said first plurality of current mirrors to effectively shut down said first programmable analog block; and

a second combination of said second plurality of local configuration bits for decreasing current through said second operational amplifier for adjusting performance of said second programmable analog block by selectively disabling current mirrors in said second plurality of current mirrors, said second combination of said second plurality of local configuration bits including disabling all current mirrors in said second plurality of current mirrors to effectively shut down said second programmable analog block.

16. The programmable analog circuit as described in claim 10, further comprising:

a microcontroller for controlling said plurality of global configuration bits, said first plurality of local configuration bits, and said second plurality of local configuration bits for providing local and global power management in said array of programmable analog blocks.

17. A method for performing local and global power management in a programmable analog circuit comprising the steps of:

asserting a plurality of global configuration bits for controlling a bias voltage for an array of programmable analog blocks coupled in parallel; and

asserting a first plurality of local configuration bits for controlling a first plurality of current mirrors coupled in parallel that adjusts performance of a first operational amplifier in a first programmable analog block in said array of programmable analog blocks.

18. The method for performing local and global power management as described in claim 17, wherein step a) further comprises the steps of:

asserting a first combination of said plurality of global configuration bits for increasing said bias voltage.

19. The method for performing local and global power management as described in claim 17, wherein step a) further comprises the steps of:

asserting a first combination of said plurality of global configuration bits for decreasing said bias voltage, said first combination of said plurality of global configuration bits including disabling all current mirrors in said first plurality of current mirrors to effectively shut down said first programmable analog block.

20. The method for performing local and global power management as described in claim 17, wherein step b) further comprises the step of:

asserting a first combination of said first plurality of local configuration bits for increasing current through said first operational amplifier for adjusting performance of said first programmable analog block by selectively enabling current mirrors in said first plurality of current mirrors.

21. The method for performing local and global power management as described in claim 17, wherein step b) further comprises the step of:

asserting a first combination of said first plurality of local configuration bits for decreasing current through said first operational amplifier for adjusting performance of said first programmable analog block by selectively disabling current mirrors in said first plurality of current mirrors, said first combination of said first plurality of local configuration bits including disabling all current mirrors in said first plurality of current mirrors to effectively shut down said first programmable analog block.

22. The method for performing local and global power management as described in claim 17, comprising the further step of:

c) asserting a second plurality of local configuration bits for controlling a second plurality of current mirrors coupled in parallel that adjusts performance of a second operational amplifier in a second programmable analog block in said array of programmable analog blocks.

23. The method for performing local and global power management as described in claim 22, wherein step c) further comprises:

asserting a second combination of said second plurality of local configuration bits for increasing current through said second operational amplifier for adjusting performance of said second programmable analog block by selectively enabling current mirrors in said second plurality of current mirrors.

24. The method for performing local and global power management as described in claim 22, wherein step c) further comprises the step of:

asserting a second combination of said second plurality of local configuration bits for decreasing current through said second operational amplifier for adjusting performance of said second programmable analog block by selectively disabling current mirrors in said second plurality of current mirrors, said second combination of said second plurality of local configuration bits including disabling all current mirrors in said second plurality of current mirrors to effectively shut down said second programmable analog block.