Large gain range, high linearity, low noise MOS VGA

• US 6,525,609 B1
• Filed: 04/12/2000
• Issued: 02/25/2003
• Est. Priority Date: 11/12/1998
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Behzad, Arya R.
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Nguyen, Khanh V.
• Application Number:
  US09/547,968
• Time in Patent Office: 1,049 Days
• Field of Search: 330/254, 327/359
• US Class Current: 330/254
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/0026 Multilayer LC-filter
• CPC Class Codes: H01F 2017/0053 with means to reduce eddy currents
• CPC Class Codes: H01F 2021/125 Printed variable inductor with taps, e.g. for VCO
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03B 2201/025 the means being an electronic switch for switching in or out oscillator elements
• CPC Class Codes: H03B 2201/0266 the means comprising a transistor
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03D 7/161 all the frequency changers being connected in cascade
• CPC Class Codes: H03D 7/18 Modifications of frequency-changers for eliminating image frequencies H03D7/16 takes precedence
• CPC Class Codes: H03F 1/3211 in differential amplifiers
• CPC Class Codes: H03G 1/0029 using FETs
• CPC Class Codes: H03H 11/1291 Current or voltage controlled filters
• CPC Class Codes: H03J 1/0075 where the receiving frequencies of the stations are stored in a permanent memory, e.g. ROM
• CPC Class Codes: H03J 2200/10 : Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 3/04 : Arrangements for compensating for variations of physical values, e.g. temperature
• CPC Class Codes: H03J 3/08 : by varying a second parameter simultaneously with the tuning, e.g. coupling bandpass filter
• CPC Class Codes: H03J 3/185 : with varactors, i.e. voltage variable reactive diodes
• CPC Class Codes: H03L 1/023 : by using voltage variable capacitance diodes
• CPC Class Codes: H03L 7/10 : for assuring initial synchronisation or for broadening the capture range
• CPC Class Codes: H03L 7/104 : using an additional signal from outside the loop for setting or controlling a parameter in the loop H03L7/107, H03L7/12 take precedence
• CPC Class Codes: H03L 7/23 : with pulse counters or frequency dividers

Abstract

An integrated receiver with channel selection and image rejection is substantially implemented on a single CMOS integrated circuit. A receiver front end provides programable attenuation and a programable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their V_ds dynamically modified in conjunction with current steering of the differential pairs sources.

Claims

1. An integrated MOS VGA having improved dynamic range, comprising:

a substrate;

a first differential pair amplifier disposed upon the substrate and coupled to a VGA output having a gain contributing to VGA gain in direct proportion to the first differential pair amplifier gain;

a second differential pair amplifier disposed upon the substrate and coupled to a VGA output having a gain, and coupled to the first differential amplifier such that an increase in second differential pair amplifier gain contributes to a decrease in the VGA gain; and

a control current split between the first differential pair amplifier and the second differential pair amplifier such that current to the second differential pair amplifier is not greater than current applied to the first differential pair amplifier and applied such that an increase in the control current causes an increase in the VGA gain.

2. The integrated MOS VGA of claim 1 further comprising:

a variable voltage source coupled to the VGA output, a voltage output of the variable voltage source determining respective drain voltages on the first differential pair and the second differential pair, and thereby controlling the gain of the first differential pair and the gain of the second differential pair;

a control signal applied to the variable voltage source to control the voltage output of the variable voltage source.

3. A method for providing, over a wide range of input signal voltages, variable gain amplification having a linear change in output current gain at a differential current output port as a function of a change in differential voltage input at a differential voltage input port, comprising the steps of:

providing an input control voltage derived from the differential input voltage;

providing a variable gain amplifier responsive to the differential input voltage, the variable gain amplifier having;

a first common source differential pair amplifier, the first common source differential pair amplifier having first common source differential pair output drains;

a second common source differential pair amplifier, the second common source differential pair amplifier having second common source differential pair output drains; and

the first common source differential pair output drains and the second common source differential pair output drains being connected in parallel to form the differential current output port and being responsive to the differential input voltage to provide the output current gain at the differential current output port;

deriving a first variable gain control signal from the input control voltage and providing the first variable control signal to the first common source differential pair amplifier to control maximizing gain of the first common source differential pair amplifier when the input control voltage is low and minimizing gain of the first common source differential pair amplifier when the input control voltage is high;

deriving a second variable gain control signal from the input control voltage and providing the second variable gain control signal to the second common source differential pair amplifier to control minimizing gain of the second common source differential pair amplifier when the input control voltage is low and maximizing gain of the second common source differential pair amplifier when the input control voltage is high;

maintaining the first gain control signal in relationship to the second gain control signal such that the second gain control signal is less than the first gain control signal; and

reducing first common source differential pair amplifier drain-source Vds voltages and second common source differential pair amplifier drain-source Vds voltages as the differential input voltage increases.

4. The method of claim 3 wherein the step of reducing includes the step of reducing absolute direct current voltage at the differential current output port.

5. The method of claim 4 wherein the step of reducing absolute direct current voltage includes the steps of:

coupling a voltage control source across the differential current output port; and

inputting a third gain control signal derived from the input control voltage to control the voltage control source to reduce absolute direct current voltage at the differential current output port as the differential input voltage increases.

6. A method for providing, over a wide range of input signal voltages, variable gain amplification having a linear change in output signal current gain as a function of a change in differential input voltage, comprising the steps of:

providing the an input control voltage derived from the differential input voltage;

providing a variable gain amplifier responsive to the differential input voltage, the variable gain amplifier having;

a first transistor, the first transistor having a first transistor gate, a first transistor source and a first transistor drain, a first transistor drain-source Vds voltage being provided across the first transistor source and first transistor drain;

a second transistor, the second transistor having a second transistor gate, a second transistor source and a second transistor drain, a second transistor drain-source Vds voltage being provided across the second transistor source and second transistor drain;

a third transistor, the third transistor having a third transistor gate, a third transistor source and a third transistor drain, a third transistor drain-source Vds voltage being provided across the third transistor source and third transistor drain;

a fourth transistor, the fourth transistor having a fourth transistor gate, a fourth transistor source and a fourth transistor drain, a fourth transistor drain-source Vds voltage being provided across the fourth transistor source and fourth transistor drain;

the first transistor gate and the fourth transistor gate being responsive to a first input voltage level of the input voltage differential, the second transistor gate and the third transistor gate being responsive to a second input voltage level, the first transistor source being coupled to the second transistor source, the third transistor source being coupled to the fourth transistor source, the second transistor drain being coupled to the fourth transistor drain to provide a first output current level of the output current differential, the first transistor drain being coupled to the third transistor drain to provide a second output current level of the output current differential;

deriving a first variable gain control signal from the control signal and providing the first variable gain control signal to the first transistor source and to the second transistor source such that both the gain of the first transistor and the gain of the second transistor can be maximized when the input control voltage is low and can be minimized when the input control voltage is high;

deriving a second variable gain control signal from the control signal and providing the second variable gain control signal to the third transistor source and to the fourth transistor source such that both a third transistor gain and a fourth transistor gain can be minimized when the input control voltage is low and can be maximized when the input control voltage is high;

maintaining the first gain control signal in relationship to the second gain control signal such that the second gain control signal is less than the first gain control signal; and

reducing the first transistor Vds voltage, the second transistor Vds voltage, the third transistor Vds voltage and the fourth transistor Vds voltage as the differential input voltage increases.

7. The method of claim 6 wherein the step of reducing includes the step of reducing absolute direct current voltage at the first transistor drain, the second transistor drain, the third transistor drain and the fourth transistor drain.

8. The method of claim 7 wherein the step of reducing absolute direct current voltage includes the steps of:

providing a fifth transistor, the fifth transistor having a fifth transistor gate, a fifth transistor source and a fifth transistor drain, the fifth transistor source being coupled to the first transistor drain and to the third transistor drain;

providing a sixth transistor, the sixth transistor having a sixth transistor gate, a sixth transistor source and a sixth transistor drain, the sixth transistor source being coupled to the second transistor drain and to the fourth transistor drain;

providing a linear amplifier, the linear amplifier having a first linear amplifier output coupled to the fifth transistor gate, a second linear amplifier output coupled to the sixth transistor gate, a first linear amplifier input being coupled to the fifth transistor drain, a second linear amplifier input being coupled to the sixth transistor drain; and

deriving a third gain control signal from the control signal to control the linear amplifier such that absolute direct current voltage at the first transistor drain, the second transistor drain, the third transistor drain and the fourth transistor drain is reduced as the differential input voltage increases.