Efficient current feedback buffer

• US 6,525,613 B2
• Filed: 05/25/2001
• Issued: 02/25/2003
• Est. Priority Date: 05/25/2001
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Cyrusian, Sasan
• Primary Examiner(s): Mis, David C.
• Application Number:
  US09/866,178
• Publication Number:
  US 20020175770A1
• Time in Patent Office: 641 Days
• Field of Search: 331/8, 331/15, 331/17, 331/18, 331/25, 331/34, 331/57, 331/177.R, 327/108, 327/109, 327/156-159
• US Class Current: 331/17
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/1806 the frequency divider comprising a phase accumulator generating the frequency divided signal

Abstract

An efficient current feedback buffer is revealed. The buffer is useful in power supplies for a number of analog and digital devices, including CMOS voltage controlled ring oscillators, frequency synthesizers, delay locked loops, phase accumulators, and phase locked loops. The power supply and buffer maintains a low impedance output to the load, regulates the voltage output of the supply, and rejects power line noise.

Claims

1. A buffered power supply, comprising:

a first transistor and a second transistor connected in series at a first point of connection;

a third transistor whose gate is connected to the first point of connection, said first and third transistors connected to a supply voltage;

a fourth transistor connected at a second point of connection to the third transistor, said second point of connection being an output terminal of the buffered power supply; and

a fifth transistor connected at a third point of connection to said third and fourth transistors, wherein the first and second transistors are a current feedback loop for the power supply.

2. The power supply of claim 1, wherein said second and fifth transistors are NMOS.

10. The power supply of claim 1, further comprising a first additional transistor connected between the first transistor and the first point of connection, and a second additional transistor connected between the third transistor and the second point of connection, wherein the first additional transistor is a part of the current feedback loop for the power supply.

11. The power supply of claim 10, wherein the first and second additional transistors are PMOS.

3. A voltage controlled oscillator, comprising:

a charge pump and loop filter;

a first buffered power supply, the buffered power supply receiving an input from the charge pump and loop filter, the buffered power supply further comprising a first transistor and a second transistor connected in series at a first point of connection;

a third transistor whose gate is connected to the first point of connection, said first and third transistors connected to a supply voltage;

a fourth transistor connected at a second point of connection to the third transistor, said second point of connection being an output terminal of the buffered power supply; and

a fifth transistor connected at a third point of connection to said third and fourth transistors, wherein the first and second transistors are a current feedback loop for the power supply; and

a voltage to frequency converter, wherein the charge pump and loop filter deliver a controlled voltage to the buffered power supply, the buffered power supply delivers a control voltage to the voltage to frequency converter, and the frequency converter generates a frequency of oscillation in accord with the voltage of the buffered power supply.

4. The voltage controlled oscillator of claim 3, wherein the control voltage is a power supply for the voltage to frequency converter.

5. The voltage controlled oscillator of claim 4, further comprising a summing resistor connected to an input line of the voltage to frequency converter, and a second buffered power supply connected to the summing resistor by a buffer amplifier of the second buffered power supply, wherein an output of the voltage controlled oscillator is determined by the sum of the voltages.

6. The voltage controlled oscillator of claim 5, wherein a gain of the first buffered power supply is different from a gain of the second buffered power supply.

7. A phase-locked loop, comprising:

a phase frequency detector;

a charge pump and loop filter connected to the phase frequency detector;

a buffered power supply, receiving an input from the charge pump and loop filter, the buffered power supply further comprising a first transistor and a second transistor connected in series at a first point of connection;

a third transistor whose gate is connected to the first point of connection, said first and third transistors connected to a supply voltage;

a fourth transistor connected at a second point of connection to the third transistor, said second point of connection being an output terminal of the buffered power supply; and

a fifth transistor connected at a third point of connection to said third and fourth transistors, wherein the first and second transistors are a current feedback loop for the power supply;

a voltage controlled oscillator powered by the power supply; and

a voltage divider connected between the oscillator and the phase frequency detector.

8. A delay locked loop, comprising:

a phase detector;

a charge pump and loop filter connected with the phase detector;

a buffered power supply receiving an input from the loop filter, said buffered power supply further comprising a first transistor and a second transistor connected in series at a first point of connection;

a third transistor whose gate is connected to the first point of connection, said first and third transistors connected to a supply voltage;

a fourth transistor connected at a second point of connection to the third transistor, said second point of connection being an output terminal of the buffered power supply; and

a fifth transistor connected at a third point of connection to said third and fourth transistors, wherein the first and second transistors are a current feedback loop for the power supply; and

a voltage controlled oscillator powered by the buffered power supply, wherein the voltage control oscillator is also connected with the phase detector.

9. A phase accumulator circuit, comprising:

a phase frequency detector;

a charge pump and loop filter, connected with the phase frequency detector;

a buffered power supply connected with the charge pump and loop filter, said buffered power supply further comprising a first transistor and a second transistor connected in series at a first point of connection;

a third transistor whose gate is connected to the first point of connection, said first and third transistors connected to a supply voltage;

a fourth transistor connected at a second point of connection to the third transistor, said second point of connection being an output terminal of the buffered power supply; and

a fifth transistor connected at a third point of connection to said third and fourth transistors, wherein the first and second transistors are a current feedback loop for the power supply;

a voltage controlled oscillator powered by the buffered power supply;

a phase accumulator, connected with the voltage controlled oscillator and receiving inputs from the oscillator;

a programmable control input, connected to the phase accumulator; and

at least one toggle flip/flop, connected to the phase accumulator and receiving inputs from the phase accumulator.

12. A buffered power supply, comprising:

a first transistor, a second transistor and a third transistor, the second and third transistors connected to the first transistor at a first point of connection;

a fourth transistor connected in series to the second transistor at a second point of connection, said second point an output terminal of the power supply; and

a fifth transistor connected in series with the third transistor at a third point of connection, said third point connected to a gate of the fourth transistor,

wherein the first transistor is connected to a positive power supply, the second transistor is connected as a source follower for the first transistor, and the third and fifth transistors are a current feedback loop.

13. The power supply of claim 12, wherein the first and third transistors are PMOS transistors.

14. The power supply of claim 12, further comprising a first additional transistor connected between the second point of connection and the fourth transistor, and a second additional transistor connected between the third point of connection and the fifth transistor, wherein the feedback loop further includes the second additional transistor.

15. The power supply of claim 12, wherein the first and second additional transistors are NMOS transistors.

16. A voltage controlled oscillator, comprising:

a charge pump and loop filter;

a first buffered power supply, the buffered power supply receiving an input from the charge pump and loop filter, the buffered power supply further comprising a first transistor and a second transistor connected in series at a first point of connection;

a third transistor whose gate is connected to the first point of connection, said first and third transistors connected to a supply voltage;

a fourth transistor connected at a second point of connection to the third transistor, said second point of connection being an output terminal of the buffered power supply; and

a fifth transistor connected at a third point of connection to said third and fourth transistors, wherein the first and second transistors are a current feedback loop for the power supply; and

a voltage to frequency converter, wherein the charge pump and loop filter deliver a controlled voltage to the buffered power supply, the buffered power supply delivers a control voltage to the voltage to frequency converter, and the frequency converter generates a frequency of oscillation in accord with the voltage of the buffered power supply.

17. The voltage controlled oscillator of claim 16 wherein the control voltage is a power supply for the voltage to frequency converter.

18. The voltage controlled oscillator of claim 17, further comprising a summing resistor connected to an input line of the voltage to frequency converter, and a second buffered power supply connected to the summing resistor by a buffer amplifier of the second buffered power supply, wherein an output of the voltage controlled oscillator is determined by the sum of the voltages.

19. The voltage controlled oscillator of claim 18, wherein a gain of the first buffered power supply is different from a gain of the second buffered power supply.

20. A phase-locked loop, comprising:

a phase frequency detector;

a charge pump and loop filter connected to the phase frequency detector;

a buffered power supply receiving an input from the charge pump and loop filter, said buffered power supply further comprising a first buffered power supply, the buffered power supply receiving an input from the charge pump and loop filter, the buffered power supply further comprising a first transistor and a second transistor connected in series at a first point of connection;

a third transistor whose gate is connected to the first point of connection, said first and third transistors connected to a supply voltage;

a fourth transistor connected at a second point of connection to the third transistor, said second point of connection being an output terminal of the buffered power supply; and

a fifth transistor connected at a third point of connection to said third and fourth transistors, wherein the first and second transistors are a current feedback loop for the power supply;

a voltage controlled oscillator powered by the power supply; and

a voltage divider connected between the oscillator and the phase frequency detector.

21. A delay locked loop, comprising:

a phase detector;

a charge pump and loop filter connected with the phase detector;

a buffered power supply receiving an input from the loop filter, said buffered power supply further comprising a first buffered power supply, the buffered power supply receiving an input from the charge pump and loop filter, the buffered power supply further comprising a first transistor and a second transistor connected in series at a first point of connection;

a third transistor whose gate is connected to the first point of connection, said first and third transistors connected to a supply voltage;

a fourth transistor connected at a second point of connection to the third transistor, said second point of connection being an output terminal of the buffered power supply; and

a fifth transistor connected at a third point of connection to said third and fourth transistors, wherein the first and second transistors are a current feedback loop for the power supply; and

a voltage controlled oscillator powered by the buffered power supply, wherein the voltage control oscillator is also connected with the phase detector.

22. A phase accumulator circuit, comprising:

a phase frequency detector;

a charge pump and loop filter, connected with the phase frequency detector;

a buffered power supply connected with the charge pump and loop filter, said buffered power supply further comprising a first buffered power supply, the buffered power supply receiving an input from the charge pump and loop filter, the buffered power supply further comprising a first transistor and a second transistor connected in series at a first point of connection;

a third transistor whose gate is connected to the first point of connection, said first and third transistors connected to a supply voltage;

a fourth transistor connected at a second point of connection to the third transistor, said second point of connection being an output terminal of the buffered power supply; and

a fifth transistor connected at a third point of connection to said third and fourth transistors, wherein the first and second transistors are a current feedback loop for the power supply;

a voltage controlled oscillator powered by the buffered power supply;

a phase accumulator, connected with the voltage controlled oscillator and receiving inputs from the oscillator;

a programmable control input, connected to the phase accumulator; and

at least one toggle flip/flop, connected to the phase accumulator and receiving inputs from the phase accumulator.

23. A buffered power supply, comprising:

a first transistor connected in series as a current source with a second transistor, a cascade device, at a first point of connection;

a third transistor whose gate is connected to the first point of connection, said first and third transistors connected to a supply voltage, said third transistor being a main current source and error amplifier;

a fourth transistor connected as a buffer amplifier at a second point of connection to the third transistor, said second point of connection being an output terminal of the buffered power supply; and

a fifth transistor connected at a third point of connection to said third and fourth transistors, said fifth transistor being a current source for the third and fourth transistors, wherein the first and second transistors are a current feedback loop for the power supply.

24. The power supply of claim 23, wherein said second and fifth transistors are NMOS.

25. The power supply of claim 23, further comprising a first additional transistor connected between the first transistor and the first point of connection, and a second additional transistor connected between the third transistor and the second point of connection, wherein the first additional transistor is a part of the current feedback loop for the power supply.

26. The power supply of claim 25, wherein the first and second additional transistors are PMOS.

27. A buffered power supply, comprising:

a first transistor, a second transistor and a third transistor, the second and third transistors connected to the first transistor at a first point of connection, wherein the first and second transistors are a current source and a source follower for the buffered power supply;

a fourth transistor connected in series to the second transistor at a second point of connection, said second point an output terminal of the power supply, the fourth transistor a main current source and error amplifier for the buffered power supply; and

a fifth transistor connected in series as a current source with the third transistor at a third point of connection, said third point connected to a gate of the fourth transistor,

wherein the first transistor is connected to a positive power supply, the second transistor is connected as a source follower for the first transistor, the third transistor is connected in series with the first transistor, and the third and fifth transistors are a current feedback loop.

28. The power supply of claim 27, wherein the first and third transistors are PMOS transistors.

29. The power supply of claim 27, further comprising a first additional transistor connected between the second point of connection and the fourth transistor, and a second additional transistor connected between the third point of connection and the fifth transistor, wherein the feedback loop further includes the second additional transistor.

30. The power supply of claim 29, wherein the first and second additional transistors are NMOS transistors.