Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication
First Claim
Patent Images
1. A memory cell comprising:
- a first conductor;
a second conductor;
a pillar having a generally rectangular first end surface comprising first spaced-apart edges and a second, opposite end surface comprising second spaced-apart edges;
the first spaced-apart edges at the first end surface being aligned with the first conductor with the first end surface being in continuous contact with the first conductor, the second spaced-apart edges at the second end surface being aligned with the second conductor with the second end surface being in continuous contact with the second conductor;
said memory cell comprising an anti-fuse layer and first and second diode components separated by the anti-fuse layer, said diode components forming a diode only after the anti-fuse layer is disrupted, said anti-fuse layer included in said pillar.
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Abstract
A three-dimensional, field-programmable, non-volatile memory includes multiple layers of first and second crossing conductors. Pillars are self-aligned at the intersection of adjacent first and second crossing conductors, and each pillar includes at least an anti-fuse layer. The pillars form memory cells with the adjacent conductors, and each memory cell includes first and second diode components separated by the anti-fuse layer. The diode components form a diode only after the anti-fuse layer is disrupted.
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Citations
49 Claims
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1. A memory cell comprising:
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a first conductor;
a second conductor;
a pillar having a generally rectangular first end surface comprising first spaced-apart edges and a second, opposite end surface comprising second spaced-apart edges;
the first spaced-apart edges at the first end surface being aligned with the first conductor with the first end surface being in continuous contact with the first conductor, the second spaced-apart edges at the second end surface being aligned with the second conductor with the second end surface being in continuous contact with the second conductor;
said memory cell comprising an anti-fuse layer and first and second diode components separated by the anti-fuse layer, said diode components forming a diode only after the anti-fuse layer is disrupted, said anti-fuse layer included in said pillar. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A memory cell comprising:
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a first conductor having a first width;
a second conductor having a second width;
a pillar having a first end surface with first opposite edges spaced-apart by a distance equal to the first width and second opposite edges spaced-apart by a distance equal to the second width, where the first opposite edges are aligned with the first conductor and the first end surface is in continuous contact with the first conductor;
said pillar having a second end surface with third opposite edges spaced-apart by a distance equal to the first width and fourth opposite edges spaced-apart by a distance equal to the second width, where the fourth opposite edges are aligned with the second conductor and the second end surface is in continuous contact with the second conductor, said memory cell comprising an anti-fuse layer and first and second diode components separated by the anti-fuse layer, said diode components forming a diode only after the anti-fuse layer is disrupted, said anti-fuse layer included in said pillar. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A memory array comprising:
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a first plurality of spaced-apart, parallel, substantially coplanar conductors;
a second plurality of spaced-apart, parallel, substantially coplanar conductors disposed generally vertically above and spaced-apart from the first conductors, said first and second conductors being generally orthogonal to one another; and
a plurality of first pillars, each first pillar directly disposed between one of the first and one of the second conductors and located where a vertical projection of the first conductors intersects the second conductors, a third plurality of spaced-apart, parallel, substantially coplanar conductors disposed generally vertically above and spaced-apart from the second conductors, the third conductors running in the same direction as the first conductors;
a plurality of second pillars, each second pillar directly disposed between one of the second conductors and one of the third conductors and located where a vertical projection of the second conductors intersects the third conductors, each of said pillars and associated conductors forming a respective memory cell, each memory cell comprising a respective anti-fuse layer and respective first and second diode components separated by the respective anti-fuse layer, each pair of said diode components forming a respective diode only after the respective anti-fuse layer is disrupted, each pillar comprising the respective anti-fuse layer. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
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34. A memory array comprising:
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a plurality of conductors on levels 1, 2, 3, 4 . . . where the levels are parallel and spaced-apart, the conductors in the odd numbered levels 1, 3 . . . running in a first direction, the levels in the even numbered levels 2, 4 . . . running in a second direction, generally perpendicular to a first direction, and a plurality of memory elements, each having an input terminal and an output terminal, the memory elements configured as respective pillars disposed between conductors in each of the levels 1, 2, 3, 4 . . . ;
the input terminals of the memory elements being directly connected to the conductors in the odd numbered levels 1, 3 . . . and the output terminals of the memory elements being directly connected to the conductors in the even numbered levels 2, 4 . . . each of said memory elements and associated conductors forming a respective memory cell, each memory cell comprising a respective anti-fuse layer and respective first and second diode components separated by the respective anti-fuse layer, each pair of said diode components forming a respective diode only after the respective anti-fuse layer is disrupted. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41)
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42. A memory array comprising:
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a plurality of conductors on levels 1, 2, 3, 4 . . . where the levels are parallel and spaced-apart, the conductors in the odd numbered levels 1,3 . . . running in a first direction, the levels in the even numbered levels 2,4 . . . running in a second direction, generally perpendicular to a first direction, and a plurality of memory elements each configured as a respective pillar having an input terminal and an output terminal;
wherein the output terminals of the memory elements are connected to the conductors in the odd numbered levels 1, 3 . . . and the input terminals of the memory elements are connected to the conductors in the even numbered levels 2, 4 . . . ;
each of said memory elements and associated conductors forming a respective memory cell, each memory cell comprising a respective anti-fuse layer and respective first and second diode components separated by the respective anti-fuse layer, each pair of said diode components forming a respective diode only after the respective anti-fuse layer is disrupted. - View Dependent Claims (43, 44, 45, 46, 47, 48, 49)
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Specification