Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication

• US 6,525,953 B1
• Filed: 08/13/2001
• Issued: 02/25/2003
• Est. Priority Date: 08/13/2001
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Johnson, Mark G.
• Primary Examiner(s): Lam, David
• Application Number:
  US09/928,536
• Time in Patent Office: 561 Days
• Field of Search: 365/63, 365/51, 365/72, 365/103, 365/105, 365/175, 365/225.7
• US Class Current: 365/63
• CPC Class Codes: G11C 17/16 using electrically-fusible links

Abstract

A three-dimensional, field-programmable, non-volatile memory includes multiple layers of first and second crossing conductors. Pillars are self-aligned at the intersection of adjacent first and second crossing conductors, and each pillar includes at least an anti-fuse layer. The pillars form memory cells with the adjacent conductors, and each memory cell includes first and second diode components separated by the anti-fuse layer. The diode components form a diode only after the anti-fuse layer is disrupted.

Claims

1. A memory cell comprising:

a first conductor;

a second conductor;

a pillar having a generally rectangular first end surface comprising first spaced-apart edges and a second, opposite end surface comprising second spaced-apart edges;

the first spaced-apart edges at the first end surface being aligned with the first conductor with the first end surface being in continuous contact with the first conductor, the second spaced-apart edges at the second end surface being aligned with the second conductor with the second end surface being in continuous contact with the second conductor;

said memory cell comprising an anti-fuse layer and first and second diode components separated by the anti-fuse layer, said diode components forming a diode only after the anti-fuse layer is disrupted, said anti-fuse layer included in said pillar.

2. The memory cell defined by claim 1 wherein the diode components comprise polysilicon.

3. The memory cell defined by claim 1 wherein the anti-fuse layer comprises a dielectric rupture anti-fuse.

4. The memory cell defined by claim 1 wherein the anti-fuse layer comprises a silicon dioxide layer sandwiched between two layers of polysilicon.

5. The memory cell defined in claim 1 wherein the anti-fuse layer comprises a silicon oxynitride layer sandwiched between two layers of polysilicon.

6. The memory cell defined by claim 1 wherein the first conductor has a width approximately equal to one dimension of the rectangular cross-section.

7. The memory cell defined by claim 6 wherein the second conductor has a width approximately equal to the other dimension of the rectangular cross-section.

8. A memory cell comprising:

a first conductor having a first width;

a second conductor having a second width;

a pillar having a first end surface with first opposite edges spaced-apart by a distance equal to the first width and second opposite edges spaced-apart by a distance equal to the second width, where the first opposite edges are aligned with the first conductor and the first end surface is in continuous contact with the first conductor;

said pillar having a second end surface with third opposite edges spaced-apart by a distance equal to the first width and fourth opposite edges spaced-apart by a distance equal to the second width, where the fourth opposite edges are aligned with the second conductor and the second end surface is in continuous contact with the second conductor,

said memory cell comprising an anti-fuse layer and first and second diode components separated by the anti-fuse layer, said diode components forming a diode only after the anti-fuse layer is disrupted, said anti-fuse layer included in said pillar.

9. The cell defined by claim 8 wherein the diode components are fabricated from polysilicon.

10. The cell defined by claim 8 wherein the diode is a metal-semiconductor Schottky diode.

11. The cell defined by claim 8 wherein the diode is a PN junction diode formed in amorphous semiconductor.

12. The cell defined by claim 8 wherein the anti-fuse layer is formed from polysilicon.

13. The cell defined by claim 8 wherein the anti-fuse layer includes silicon dioxide.

14. The cell defined by claim 8 wherein the anti-fuse layer includes silicon oxynitride.

15. The cell defined by claim 8 wherein the anti-fuse layer is a dielectric-rupture anti-fuse.

16. The cell defined by claim 8 wherein the anti-fuse layer is a polycrystalline semiconductor anti-fuse.

17. The cell defined by claim 8 wherein the anti-fuse layer is an amorphous semiconductor anti-fuse.

18. The cell defined by claim 8 where the diode is able to carry a sufficient current to change the state of the anti-fuse layer.

19. The cell defined by claim 8 wherein the diode components comprise recrystallized semiconductor.

20. The cell defined by claim 8 wherein the diode components and the anti-fuse layer include amorphous silicon.

21. The cell defined by claim 8 wherein one of the terminals of the cell is connected to a word line.

22. The cell defined by claim 21 wherein the other of the terminals of the cell is connected to a bit line.

23. A memory array comprising:

a first plurality of spaced-apart, parallel, substantially coplanar conductors;

a second plurality of spaced-apart, parallel, substantially coplanar conductors disposed generally vertically above and spaced-apart from the first conductors, said first and second conductors being generally orthogonal to one another; and

a plurality of first pillars, each first pillar directly disposed between one of the first and one of the second conductors and located where a vertical projection of the first conductors intersects the second conductors,

a third plurality of spaced-apart, parallel, substantially coplanar conductors disposed generally vertically above and spaced-apart from the second conductors, the third conductors running in the same direction as the first conductors;

a plurality of second pillars, each second pillar directly disposed between one of the second conductors and one of the third conductors and located where a vertical projection of the second conductors intersects the third conductors,

each of said pillars and associated conductors forming a respective memory cell, each memory cell comprising a respective anti-fuse layer and respective first and second diode components separated by the respective anti-fuse layer, each pair of said diode components forming a respective diode only after the respective anti-fuse layer is disrupted, each pillar comprising the respective anti-fuse layer.

24. The array defined by claim 23 wherein the cells of the first and second pillars are in vertical alignment with one another.

25. The array defined by claim 23 wherein the cells of the first and second pillars are staggered from one another.

26. The array defined by claim 23 wherein the cells have a generally rectangular cross-section.

27. The array defined by claim 23 wherein the cells comprise polysilicon and silicon dioxide.

28. The array defined in claim 23 wherein the cells comprise. polysilicon and silicon oxynitride.

29. The array defined by claim 23 wherein the cells comprise polysilicon.

30. The array defined by claim 23 wherein the array is fabricated on a silicon substrate.

31. The array defined by claim 23 wherein the first and second conductors include a refractory metal.

32. The array defined by claim 31 wherein the refractory metal is tungsten.

33. The array defined by claim 23 wherein the first and second conductors are a silicide.

34. A memory array comprising:

a plurality of conductors on levels 1, 2, 3, 4 . . . where the levels are parallel and spaced-apart, the conductors in the odd numbered levels 1, 3 . . . running in a first direction, the levels in the even numbered levels 2, 4 . . . running in a second direction, generally perpendicular to a first direction, and

a plurality of memory elements, each having an input terminal and an output terminal, the memory elements configured as respective pillars disposed between conductors in each of the levels 1, 2, 3, 4 . . . ;

the input terminals of the memory elements being directly connected to the conductors in the odd numbered levels 1, 3 . . . and the output terminals of the memory elements being directly connected to the conductors in the even numbered levels 2, 4 . . .

each of said memory elements and associated conductors forming a respective memory cell, each memory cell comprising a respective anti-fuse layer and respective first and second diode components separated by the respective anti-fuse layer, each pair of said diode components forming a respective diode only after the respective anti-fuse layer is disrupted.

35. The array defined by claim 34 wherein the cells have a generally rectangular cross-section.

36. The array defined by claim 34 wherein the cells comprise silicon and silicon dioxide.

37. The array defined by claim 34 wherein the cells comprise silicon and silicon oxynitride.

38. The array defined by claim 34 wherein the conductors of levels 1, 3 . . . are in vertical alignment with one another.

39. The array defined by claim 34 wherein the conductors in one of the sets of levels 1, 3 . . . and levels 2, 4 . . . are staggered in the vertical direction.

40. The array defined by claim 34 wherein the conductors comprise polysilicon.

41. The array defined by claim 34 wherein the array is fabricated on a silicon substrate.

42. A memory array comprising:

a plurality of conductors on levels 1, 2, 3, 4 . . . where the levels are parallel and spaced-apart, the conductors in the odd numbered levels 1,3 . . . running in a first direction, the levels in the even numbered levels 2,4 . . . running in a second direction, generally perpendicular to a first direction, and

a plurality of memory elements each configured as a respective pillar having an input terminal and an output terminal;

wherein the output terminals of the memory elements are connected to the conductors in the odd numbered levels 1, 3 . . . and the input terminals of the memory elements are connected to the conductors in the even numbered levels 2, 4 . . . ;

each of said memory elements and associated conductors forming a respective memory cell, each memory cell comprising a respective anti-fuse layer and respective first and second diode components separated by the respective anti-fuse layer, each pair of said diode components forming a respective diode only after the respective anti-fuse layer is disrupted.

43. The array defined by claim 42 wherein the cells have a generally rectangular cross-section.

44. The array defined by claim 42 wherein the cells comprise silicon and silicon dioxide.

45. The array defined by claim 42 wherein the cells comprise silicon and silicon oxynitride.

46. The array defined by claim 42 wherein the conductors of levels 1, 3 . . . are in vertical alignment with one another.

47. The array defined by claim 42 wherein the conductors in one of the sets of levels 1, 3 . . . and levels 2, 4 . . . are staggered in the vertical direction.

48. The array defined by claim 42 wherein the conductors comprise polysilicon.

49. The array defined by claim 42 wherein the array is fabricated on a silicon substrate.