Method and apparatus for a dense metal programmable ROM

• US 6,525,954 B2
• Filed: 06/28/2001
• Issued: 02/25/2003
• Est. Priority Date: 09/29/2000
• Status: Expired due to Term

• Current Assignee: Arm Incorporated (SoftBank Group Corp.)
• Original Assignee: Artisan Components, Inc. (SoftBank Group Corp.)
• Inventors: Becker, Scott T.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US09/896,444
• Publication Number:
  US 20020039305A1
• Time in Patent Office: 607 Days
• Field of Search: 365/63, 365/94, 365/185.01, 365/185.05, 365/185.11, 257/390
• US Class Current: 365/94
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/34 Source electrode or drain electrode programmed

Abstract

A metal programmable ROM is disclosed that includes a memory cell array having a depth that is defined by a plurality of wordlines and a width that is defined by a plurality of bitlines. In addition, a group of memory cells are coupled between a bitline and ground, with each memory cell in the memory cell group coupled to at least one other memory cell in the memory cell group. Finally, a programmed memory cell is included that is defined by a memory cell transistor having its terminals shorted together.

Claims

1. A metal programmable ROM, comprising:

a memory cell array having a plurality of wordlines and a plurality of bitlines; and

a first group of transistors coupled to a first subset of wordlines of the plurality of wordlines, comprising;

a first transistor having a first terminal and a second terminal, the first terminal being coupled to a bitline of the plurality of bitlines, and a first gate terminal coupled to a first wordline of the first subset of wordlines; and

a second transistor having a first terminal and a second terminal, the second terminal being coupled to a first ground, and a second gate terminal coupled to a second wordline of the first subset of wordlines,

wherein at least one programmed transistor in the first group of transistors includes a first terminal, a second terminal, and gate region coupled to a particular wordline of the first subset of wordlines, wherein the first terminal and the second terminal are shorted together.

2. A metal programmable ROM as recited in claim 1, further comprising a third transistor having a first terminal and a second terminal, the first terminal being coupled to the second terminal of the first transistor, and a third gate terminal being coupled to a third wordline of the first subset of wordlines.

3. A metal programmable ROM as recited in claim 2, further comprising a fourth transistor having a first terminal and a second terminal, the first terminal being coupled to the second terminal of the third transistor, the second terminal being coupled to the first terminal of the second transistor, and a fourth gate terminal being coupled to a fourth wordline of the first subset of wordlines.

4. A metal programmable ROM as recited in claim 3, wherein a selected wordline in the first subset of wordlines is pulled low, and wherein all other wordlines in the first subset of wordlines are asserted high.

5. A metal programmable ROM as recited in claim 4, wherein all wordlines outside the first subset of wordlines are pulled low.

6. A metal programmable ROM as recited in claim 1, wherein all transistors in the first group of transistors are embodied on a single portion of diffusion material.

7. A metal programmable ROM as recited in claim 1, wherein the bitline is pulled low when the particular wordline coupled to the gate of the shorted transistor is selected.

8. A metal programmable ROM as recited in claim 7, wherein a metal containing material couples the first terminal and the second terminal of the programmed transistor.

9. A metal programmable ROM as recited in claim 1, further comprising a second group of transistors coupled to a second subset of wordlines of the plurality of wordlines, comprising:

a third transistor having a first terminal and a second terminal, the first terminal being coupled to the bitline, and a third gate terminal coupled to a third wordline of the second subset of wordlines; and

a fourth transistor having a first terminal and a second terminal, the second terminal being coupled to a second ground, and a fourth gate terminal coupled to a fourth wordline of the second subset of wordlines.

10. A metal programmable ROM, comprising:

a memory cell array having a plurality of wordlines and a plurality of bitlines;

a first group of transistors coupled to a first subset of wordlines of the plurality of wordlines, comprising;

a first transistor having a first terminal and a second terminal, the first terminal being coupled to a bitline of the plurality of bitlines, and a first gate terminal coupled to a first wordline of the first subset of wordlines; and

a second transistor having a first terminal and a second terminal, the second terminal being coupled to a first ground, and a second gate terminal coupled to a second wordline of the first subset of wordlines; and

a second group of transistors coupled to a second subset of wordlines of the plurality of wordlines, comprising;

a third transistor having a first terminal and a second terminal, the first terminal being coupled to the bitline, and a third gate terminal coupled to a third wordline of the second subset of wordlines; and

a fourth transistor having a first terminal and a second terminal, the second terminal being coupled to a second ground, and a fourth gate terminal coupled to a fourth wordline of the second subset of wordlines,

wherein at least one programmed transistor in the first group of transistors includes a first terminal, a second terminal, and gate region coupled to a particular wordline of the first subset of wordlines, wherein the first terminal and the second terminal are shorted together.

11. A metal programmable ROM as recited in claim 10, further comprising a fifth transistor having a first terminal and a second terminal, the first terminal being coupled to the second terminal of the first transistor, and a fifth gate terminal being coupled to a fifth wordline of the first subset of wordlines.

12. A metal programmable ROM as recited in claim 11, further comprising a sixth transistor having a first terminal and a second terminal, the first terminal being coupled to the second terminal of the fifth transistor, the second terminal being coupled to the first terminal of the second transistor, and a sixth gate terminal being coupled to a sixth wordline of the first subset of wordlines.

13. A metal programmable ROM as recited in claim 10, wherein all transistors in the first group of transistors are embodied on a single portion of diffusion material.

14. A metal programmable ROM as recited in claim 10, wherein the bitline is pulled low when the particular wordline coupled to the gate of the shorted transistor is selected.

15. A metal programmable ROM as recited in claim 14, wherein a metal containing material couples the first terminal and the second terminal of the programmed transistor.

16. A metal programmable ROM, comprising:

a memory cell array having a plurality of wordlines and a plurality of bitlines;

a group of transistors coupled between a bitline and ground, wherein each transistor functions as a memory cell, and wherein each transistor in the group of transistors is coupled to at least one other transistor in the group of transistors; and

a programmed transistor having a first terminal and second terminal shorted together, the programmed transistor functioning as a programmed memory cell.

17. A metal programmable ROM as recited in claim 16, wherein each transistor is coupled to a corresponding wordline in the plurality of wordlines.

18. A metal programmable ROM as recited in claim 17, wherein each transistor includes a first terminal, a second terminal, and gate coupled to a wordline corresponding to the transistor.

19. A metal programmable ROM as recited in claim 18, wherein a first transistor of the group of transistors includes a first terminal and a second terminal, wherein the first terminal is coupled to the bitline.