High current and/or high speed electrically erasable memory cell for programmable logic devices

• US 6,525,962 B1
• Filed: 04/05/2000
• Issued: 02/25/2003
• Est. Priority Date: 04/05/2000
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Pai, Sheng-Yueh, Chen, Yue, Yen, Kevin
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US09/543,462
• Time in Patent Office: 1,056 Days
• Field of Search: 365/185.09, 365/185.05, 257/314, 257/315, 257/316, 257/317, 257/319, 257/320, 257/390
• US Class Current: 365/185.09
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An electrically erasable programmable logic device (EEPLD) cell (100) is disclosed. A folded floating gate (110) and folded select gate (108) can form two parallel read current paths (Isense0 and Isense1). A first read current path (Isense0) may be formed between a first semiconductor region (104) and a second semiconductor region (106-0), and may be controlled by a first floating gate portion (110-0) and a first select gate portion (108-0). A second read current path (Isense1) may be formed between the first semiconductor region (104) and a third semiconductor region (106-1) that is coupled to a second semiconductor region (106-0). A second read current path (Isense1) may be controlled by a second floating gate portion (110-1) and a second select gate portion (108-1).

Claims

1. A programmable logic device (PLD) storage element, comprising:

a floating gate having a first portion between a first semiconductor region and a second semiconductor region and a second portion between the first semiconductor region and a third semiconductor region, the second semiconductor region being connected to the third semiconductor region; and

a select gate having a first portion between the first semiconductor region and the second semiconductor region and a second portion between the first semiconductor region and the third semiconductor region.

2. The PLD storage element of claim 1, wherein:

the floating gate first portion is physically parallel to the select gate first portion.

3. The PLD storage element of claim 2, wherein:

the floating gate second portion is physically parallel to the select gate second portion.

4. The PLD storage element of claim 1, further including:

at least one logic circuit gate having a minimum logic circuit gate length; and

the floating gate has a gate length less than the minimum logic circuit gate length.

5. The PLD storage element of claim 1, further including:

at least one logic circuit gate having a minimum logic circuit gate length; and

the select gate has a gate length less than the minimum logic circuit gate length.

6. The PLD storage element of claim 1, further including:

at least one logic circuit having a transistor diffusion region with a first doping concentration; and

a select gate diffusion region adjacent to the select gate with a doping concentration less than the first doping concentration.

7. The PLD storage element of claim 1, further including:

at least one logic circuit having a transistor diffusion region with a first doping concentration; and

a floating gate diffusion region adjacent to the select gate with a doping concentration less than the first doping concentration.

8. A programmable logic circuit, comprising:

a first current path having an impedance controlled by a first portion of a select gate and a first portion of a floating gate; and

a second current path electrically parallel to the first current path having an impedance controlled by a second portion of the select gate and a second portion of the floating gate.

9. The programmable logic circuit of claim 8, further including:

a first gate insulator between the select gate and a substrate; and

a second gate insulator between the floating gate and the substrate, the second gate insulator thickness being greater than that of the first gate insulator.

10. The programmable logic circuit of claim 8, wherein:

the first current path is disposed between a first contact and a second contact; and

the second current path is disposed between the first contact and a third contact that is coupled to the second contact.

11. The programmable logic circuit of claim 8, further including:

a tunneling region below the floating gate.

12. The programmable logic circuit of claim 11, further including:

a programming transistor for controlling the tunneling region, the programming transistor being capable of receiving a voltage that is greater than a supply voltage for the programmable logic circuit.

13. The programmable logic circuit of claim 11, wherein:

the floating gate includes a coupling capacitor portion having an area that is larger than the area of the tunneling region.

14. The programmable logic circuit of claim 8, wherein:

the first and second portions of the select gate are situated between the first and second portions of the floating gate.

15. A non-volatile electrically erasable programmable logic device (EEPLD) cell, comprising:

a select gate and a floating gate that control the conductivity between a first substrate region and two physically separate but electrically connected second substrate regions.

16. The EEPLD cell of claim 15, further including:

a select gate first portion and floating gate first portion electrically in series between the first substrate region and one of the second substrate regions; and

a select gate second portion and floating gate second portion electrically in series between the first substrate region and the other of the second substrate regions.

17. The EEPLD cell of claim 16, wherein:

the select gate first portion is electrically in series with the select gate second portion.

18. The EEPLD cell of claim 15, wherein:

the EEPLD cell is part of a PLD having a plurality of logic gates with at least one minimum logic transistor gate length; and

the select gate has gate length less than the minimum logic transistor gate length.

19. The EEPLD cell of claim 15, further including:

the EEPLD cell is part of a PLD having a plurality of logic gates with at least one logic transistor having source and drain regions with a minimum lateral diffusion size; and

a current path diffusion region between one portion of a floating gate and an adjacent portion of a select gate, the current path diffusion region having a smaller lateral diffusion size than the minimum lateral diffusion size.

20. The EEPLD cell of claim 15, wherein:

the floating gate and select gate are formed from the same layer of polycrystalline silicon.