Distributed write data drivers for burst access memories

• US 6,525,971 B2
• Filed: 07/27/1999
• Issued: 02/25/2003
• Est. Priority Date: 06/30/1995
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy A., Merritt, Todd A.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US09/361,795
• Publication Number:
  US 20020001234A1
• Time in Patent Office: 1,309 Days
• Field of Search: 365/230.01, 365/189.01, 365/233.5, 365/189.05, 365/193, 365/233, 365/202, 365/204, 713/500, 713/503, 395/555, 395/558
• US Class Current: 365/189.05
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1024 Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
• CPC Class Codes: G11C 7/1027 Static column decode serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled bit line addresses
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies. Local logic gates near array sense amplifiers are used to control write data drivers to provide for maximum write times without crossing current during input/output line equilibration periods. By gating global write enable signals with global equilibrate signals locally at data sense amp locations, local write cycle control signals are provided which are valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory devices. For nonburst mode memory devices such as EDO and Fast Page Mode, the write function may begin immediately following the end of the equilibration cycle to provide a maximum write time without interfering with the address setup time of the next access cycle.

Claims

1. A system comprising:

a processing unit; and

memory device coupled to the processing unit and comprising;

a data input;

a plurality of memory element subarrays;

a plurality of data sense amplifiers coupled to the subarrays, each of the data sense amplifiers comprising a write data driver responsive to an active write enable signal and an active equilibration signal, to drive write data received on the data input to a corresponding one of the subarrays;

an address strobe input; and

an output buffer coupled to at least two of the data sense amplifiers and to the address strobe input, the output buffer adapted to drive data from the memory device in response to an address strobe signal after a latency of at least one active transition of the address strobe signal in a burst read access.

2. The system of claim 1 wherein the processing unit comprises a single microprocessor.

3. A system comprising:

a processing unit; and

memory device coupled to the processing unit and comprising;

a plurality of internal data line pairs;

an equilibration control circuit;

a write cycle control circuit;

one or more data sense amplifiers each coupled to the equilibration control circuit, the write cycle control circuit, and at least one of the data line pairs;

one or more write data drivers, each write data driver associated with at least one of the data sense amplifiers;

one or more write data driver enable circuits, each write driver enable circuit responsive to deassertion of an equilibrate signal from the equilibration control circuit during assertion of a write cycle enable signal from the write cycle control circuit to enable at least one of the write data drivers to drive data onto at least one of the data line pairs; and

a burst access control circuit responsive to an access cycle strobe signal to receive an initial address and to generate a series of addresses, each in response to subsequent transition of the access cycle strobe signal.

4. The system of claim 3 wherein the processing unit comprises a single microprocessor.

12. The system of claim 3, wherein each write driver enable circuit comprises:

a first logic gate having a first input for receiving the write cycle enable signal, a second input for receiving a signal based on assertion of a row address, and an output;

a second logic gate having a first input coupled to the output of the first logic gate, a second input for receiving the equilibrate signal, and an output for providing a write enable signal;

an inverter having an input coupled to the output of the second logic gate and an output for providing an inverse of the write enable signal;

a third logic gate having a first input coupled to receive a write data signal, a second input coupled to receive the inverse of the write enable signal, and an output coupled to control one write data driver in one of the pairs of write data drivers; and

a fourth logic gate having a first input coupled to receive the write data signal, a second input coupled to receive the write enable signal, and an output coupled to control the other write data driver in the one of the pairs of write data drivers.

5. A system comprising:

a processing unit; and

memory device coupled to the processing unit and comprising;

a plurality of internal data line pairs;

an equilibration control circuit;

a write cycle control circuit;

one or more data sense amplifiers each coupled to the equilibration control circuit, the write cycle control circuit and at least one of the data line pairs;

one or more write data drivers, each write data driver associated with at least one of the data sense amplifiers;

one or more write data driver enable circuits, each write driver enable circuit responsive to deassertion of an equilibrate signal from the equilibration control circuit during assertion of a write cycle enable signal from the write cycle control circuit to enable at least one of the write data drivers to drive data onto at least one of the data line pairs;

a burst access control circuit responsive to an access cycle strobe signal to receive an initial address and to generate a series of addresses, each in response to subsequent transition of the access cycle strobe signal; and

an output buffer coupled to at least one of the data sense amplifiers and responsive to one or more transitions of the access cycle strobe signal to drive data from the memory device.

13. The system of claim 5, wherein each write driver enable circuit comprises:

a first logic gate having a first input for receiving the write cycle enable signal, a second input for receiving a signal based on assertion of a row address, and an output;

a second logic gate having a first input coupled to the output of the first logic gate, a second input for receiving the equilibrate signal, and an output for providing a write enable signal;

an inverter having an input coupled to the output of the second logic gate and an output for providing an inverse of the write enable signal;

a third logic gate having a first input coupled to receive a write data signal, a second input coupled to receive the inverse of the write enable signal, and an output coupled to control one write data driver in one of the pairs of write data drivers; and

a fourth logic gate having a first input coupled to receive the write data signal, a second input coupled to receive the write enable signal, and an output coupled to control the other write data driver in the one of the pairs of write data drivers.

6. A system comprising:

a processing unit; and

memory device coupled to the processing unit and comprising;

one or more write data drivers comprising an enable input, a data input, and a data output;

one or more data lines, each of the data lines coupled to the data output of at least one of the write data drivers;

one or more write data driver enable circuits, each of the write data driver enable circuits responsive to a write cycle control signal and an equilibrate control signal to apply a signal to the enable input of one or more of the write data drivers; and

one or more data sense amplifiers, each of the data sense amplifiers being associated with one of the plurality of write data drivers.

14. The system of claim 6, wherein each write driver enable circuit comprises:

a first logic gate having a first input for receiving the write cycle enable signal, a second input for receiving a signal based on assertion of a row address, and an output;

a second logic gate having a first input coupled to the output of the first logic gate, a second input for receiving the equilibrate signal, and an output for providing a write enable signal;

an inverter having an input coupled to the output of the second logic gate and an output for providing an inverse of the write enable signal;

a third logic gate having a first input coupled to receive a write data signal, a second input coupled to receive the inverse of the write enable signal, and an output coupled to control one write data driver in one of the pairs of write data drivers; and

a fourth logic gate having a first input coupled to receive the write data signal, a second input coupled to receive the write enable signal, and an output coupled to control the other write data driver in the one of the pairs of write data drivers.

7. A system comprising:

a processing unit; and

memory device coupled to the processing unit and comprising;

a memory element array region;

a control circuit region, outside of the memory element array region, for generating memory control signals including an equilibrate signal and a write enable signal;

one or more data line pairs distributed within the memory element array region;

one or more data sense amplifiers distributed along an edge of the memory element array region, each amplifier located near at least one of the data line pairs; and

a distributed plurality of write data drivers each comprising an equilibrate inactive input enable responsive to the equilibrate signal and a write active input enable responsive to the write enable signal, each of the write data drivers located near to a data sense amplifier and associated with at least one of the data line pairs.

8. A system comprising:

a processing unit; and

memory device coupled to the processing unit and comprising;

a data input;

two or more memory element subarrays; and

at least first and second data-sensing-and-amplifying means coupled to the subarrays, each data-sensing-and-amplifying means comprising write data driving means responsive to an active write enable signal and an inactive equilibration signal to drive write data received on the data input to at least one of the subarrays.

9. A system comprising:

a processing unit; and

memory device coupled to the processing unit and comprising;

a plurality of internal data line pairs;

an equilibration control circuit;

a write cycle control circuit;

data-sense-amplification means coupled to the equilibration control circuit, the write cycle control circuit and at least one of the data line pairs for sensing data;

write-data-driving means associated with the data-sense-amplification means; and

enabling means responsive to deassertion of an equilibrate signal from the equilibration control circuit during assertion of a write cycle enable signal from the write cycle control circuit to enable the write-data-driving means to drive data onto at least one of the data line pairs.

10. A system comprising:

a processor; and

a memory device coupled to the processor and responsive to a write cycle command from the microprocessor, with the memory device comprising;

a write cycle control input coupled to the processor;

a data input coupled to the processor;

a plurality of distributed internal data lines;

a plurality of distributed internal write data drivers coupled to the data input and to the distributed internal data lines, with each of the write data drivers comprising an equilibration signal input, a write signal input, a write data input, and a write data output; and

a plurality of write data driver enable circuits located in close proximity and coupled to the write data drivers.

11. The system of claim 10, wherein the memory device is a Burst Extended Data Out Dynamic Random Access Memory.

15. A system comprising:

a processing unit; and

at least one memory device coupled to the processing unit and comprising;

a plurality of internal data line pairs;

one or more equilibration devices, with each equilibration device coupled between a respective one of the data line pairs;

one or more pairs of write data drivers, with each pair for driving one data line in at least one of the data line pairs;

one or more write data driver enable circuits, each write driver enable circuit responsive to deassertion of an equilibrate signal during assertion of a write cycle enable signal to enable at least one of the write data drivers to drive data onto at least one of the data line pairs, each write driver enable circuit comprising;

a first logic gate having a first input for receiving the write cycle enable signal, a second input for receiving a signal based on assertion of a row address, and an output;

a second logic gate having a first input coupled to the output of the first logic gate, a second input for receiving the equilibrate signal, and an output for providing a write enable signal;

an inverter having an input coupled to the output of the second logic gate and an output for providing an inverse of the write enable signal;

a third logic gate having a first input coupled to receive a write data signal, a second input coupled to receive the inverse of the write enable signal, and an output coupled to control one write data driver in one of the pairs of write data drivers; and

a fourth logic gate having a first input coupled to receive the write data signal, a second input coupled to receive the write enable signal, and an output coupled to control the other write data driver in the one of the pairs of write data drivers.

16. The system of claim 15, wherein each equilibration device comprises a single field-effect transistor.

17. The system of claim 15, wherein each pair of write data drivers comprises a pair of field-effect transistors.

18. The system of claim 15, wherein each of the first, second, and third logic gates comprises a NAND gate, and the fourth logic gate comprises a NOR gate.

19. A system comprising:

a processing unit; and

at least one memory device coupled to the processing unit and comprising;

a plurality of internal data line pairs;

one or more equilibration devices, with each equilibration device coupled between a respective one of the data line pairs;

one or more pairs of write data drivers, with each pair for driving one data line in at least one of the data line pairs;

one or more write data driver enable circuits, each write driver enable circuit responsive to deassertion of an equilibrate signal during assertion of a write cycle enable signal to enable at least one of the write data drivers to drive data onto at least one of the data line pairs, each write driver enable circuit comprising;

a first logic gate having a first input for receiving the write cycle enable signal, a second input for receiving a signal based on assertion of a row address, and an output;

a second logic gate having a first input coupled to the output of the first logic gate, a second input for receiving the equilibrate signal, and an output for providing a write enable signal;

an inverter having an input coupled to the output of the second logic gate and an output for providing an inverse of the write enable signal;

a third logic gate having a first input coupled to receive a write data signal, a second input coupled to receive the inverse of the write enable signal, and an output coupled to control one write data driver in a first one of the pairs of write data drivers;

a fourth logic gate having a first input coupled to receive the write data signal, a second input coupled to receive the write enable signal, and an output coupled to control the other write data driver in the first one of the pairs of write data drivers;

a fifth logic gate having a first input coupled to receive an inverse of the write data signal, a second input coupled to receive the inverse of the write enable signal, and an output coupled to control one write data driver in a second one of the pairs of write data drivers; and

a sixth logic gate having a first input coupled to receive an inverse of the write data signal, a second input coupled to receive the write enable signal, and an output coupled to control the other write data driver in the second one of the pairs of write data drivers.

20. The system of claim 19, wherein each equilibration device comprises a single field-effect transistor.

21. The system of claim 19, wherein each pair of write data drivers comprises a pair of field-effect transistors.

22. The system of claim 19, wherein each of the first, second, third, and fifth logic gates comprises a NAND gate, and each of the fourth and sixth logic gate comprises a NOR gate.

23. A system comprising:

a processing unit; and

at least one memory device coupled to the processing unit and comprising;

a plurality of internal data line pairs;

one or more equilibration devices, with each equilibration device coupled between a respective one of the data line pairs;

one or more pairs of write data drivers, with each pair for driving one data line in at least one of the data line pairs;

one or more write data driver enable circuits, each write driver enable circuit responsive to deassertion of an equilibrate signal during assertion of a write cycle enable signal to enable at least one of the write data drivers to drive data onto at least one of the data line pairs, each write driver enable circuit comprising;

a first NAND gate having a first input for receiving the write cycle enable signal, a second input for receiving a signal based on assertion of a row address, and an output;

a second NAND gate having a first input coupled to the output of the first NAND gate, a second input for receiving the equilibrate signal, and an output for providing a write enable signal;

an inverter having an input coupled to the output of the second NAND gate and an output for providing an inverse of the write enable signal;

a third NAND gate having a first input coupled to receive a write data signal, a second input coupled to receive the inverse of the write enable signal, and an output coupled to control one write data driver in a first one of the pairs of write data drivers;

a first NOR gate having a first input coupled to receive the write data signal, a second input coupled to receive the write enable signal, and an output coupled to control the other write data driver in the first one of the pairs of write data drivers;

a fourth NAND gate having a first input coupled to receive an inverse of the write data signal, a second input coupled to receive the inverse of the write enable signal, and an output coupled to control one write data driver in a second one of the pairs of write data drivers; and

a second NOR gate having a first input coupled to receive an inverse of the write data signal, a second input coupled to receive the write enable signal, and an output coupled to control the other write data driver in the second one of the pairs of write data drivers.

24. The system of claim 23, wherein each equilibration device comprises a single field-effect transistor.

25. The system of claim 23, wherein each pair of write data drivers comprises a pair of field-effect transistors.

26. The system of claim 23, wherein each gate has only two inputs.