Semiconductor memory device with boosting control circuit and control method

• US 6,525,972 B2
• Filed: 07/05/2001
• Issued: 02/25/2003
• Est. Priority Date: 07/06/2000
• Status: Expired due to Term

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: NEC Corporation
• Inventors: Yanagisawa, Takeshi
• Primary Examiner(s): Tran, Andrew Q.
• Application Number:
  US09/899,779
• Publication Number:
  US 20010050878A1
• Time in Patent Office: 600 Days
• Field of Search: 365/189.09, 365/230.06, 365/228, 365/226, 365/233.5, 365/194, 365/195, 365/191, 365/189.07, 326/88, 327/536, 327/537, 327/534, 327/530
• US Class Current: 365/189.09
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/70 time intervals between all adjacent pulses of one train being equal

Abstract

A semiconductor memory device (50) having a boosted potential generation circuit is provided. The boosted potential generation circuit may provide charge to a boosted potential node when a word line (11) is to be activated. The boosted potential generation circuit may include a boosting control circuit (5), a boosted potential detection circuit (6), an oscillator circuit (7), and a booster circuit (8). The boosting control circuit (5) may generate a boosting control signal when a command decoder (1) indicates that a word line may be activated. In response to the boosting control signal, the boosted potential detection circuit (6) may enable the oscillator circuit (7) so that booster circuit (8) may transfer charge to the boosted potential node. This may allow the boosted potential node to have adequate charge that may be provided to the word line when activated.

Claims

1. A semiconductor memory device, comprising:

a memory cell array having a plurality of word lines;

a word selection circuit that activates one of the plurality of word lines based on the value of an address;

a boosted potential coupled to the word selection circuit, the boosted potential providing charge to the activated word line; and

a boosted potential generation circuit coupled to provide the boosted potential, the boosted potential generation circuit providing charge to the boosted potential when the word line is to be activated.

2. The semiconductor memory device according to claim 1, wherein:

the boosted potential generation circuit detects a command to activate a word line and provides charge to the boosted potential before the word line is activated.

3. The semiconductor memory device according to claim 2, wherein:

the command to activate a word line is a read command or a write command.

4. The semiconductor memory device according to claim 2, wherein:

the command to activate a word line is a refresh command.

5. The semiconductor memory device according to claim 1, wherein the boosted potential generation circuit includes:

an oscillator circuit coupled to generate an oscillation signal;

a booster circuit coupled to provide charge to the boosted potential in response to the oscillation signal;

a boosting control circuit coupled to provide a one-shot boosting control signal indicating that the word line is to be activated; and

a boosted potential detection circuit coupled to receive the one-shot boosting control signal and provide a boosted voltage signal having an oscillator enable state and an oscillator disable state.

6. The semiconductor memory device according to claim 5, wherein:

the boosted voltage signal has the oscillator enable state when the one-shot boosting control signal indicates that the word line is to be activated; and

the boosted voltage signal has the oscillator enable state when the boosted potential is lower than a predetermined potential.

7. The semiconductor memory device according to claim 5, wherein:

the boosted voltage signal has the oscillator enable state when the boosted potential is lower than a first predetermined potential when the one-shot boosting control signal does not indicate that the word line is to be activated;

the boosted voltage signal has the oscillator enable state when the boosted potential is lower than a second predetermined potential when the one-shot boosting control signal indicates that the word line is to be activated; and

the second predetermined potential is greater than the first predetermined potential.

8. The semiconductor memory device according to claim 5, wherein:

the oscillator circuit includes an oscillating signal generator and an oscillator preset circuit;

the oscillating signal generator oscillates when the boosted voltage signal is in the oscillator enable state; and

the oscillator preset circuit presets the oscillating signal generator to an opposite start state when the boosted voltage signal is in the oscillator disable state.

9. A control method for controlling a semiconductor memory device having a booster circuit that generates a boosted potential in response to an oscillation signal generated by an oscillator circuit, the method comprising the steps of:

receiving a command and an address;

decoding the command;

generating a boosting control signal in response to the decoded command indicating that a word line is to be activated;

providing charge to a boosted potential node in response to the boosting control signal; and

providing an electrical connection between the boosted potential node and the word line in accordance with the value of the address received.

10. The control method according to claim 9, wherein:

the step of providing charge to the boosted potential node provides a boosted potential greater than an activation potential of the word line.

11. The control method according to claim 9, wherein:

the step of generating a boosting control signal includes generating a one-shot pulse.

12. The control method according to claim 9, wherein:

the step of providing charge to a boosted potential node includes generating the oscillation signal in response to the boosting control signal; and

the oscillation signal has an oscillation signal period between transitions.

13. The control method according to claim 12, wherein:

generating the oscillation signal in response to the boosting control signal includes generating an oscillation control signal in response to the boosting control signal; and

the oscillation signal has a last oscillation state when the oscillation control signal is in an oscillation disable state and the oscillation signal transitions to an opposite to last oscillation state when the oscillation control signal transitions to an oscillation enable state without being delayed by the oscillation signal period between transitions.

14. A semiconductor memory device, comprising:

a memory cell array having a plurality of word lines;

a word selection circuit that activates one of the plurality of word lines based on an address value;

a boosting control circuit coupled to generate a boosting control signal in response to a control signal indicating that a word line is to be activated;

a boosted potential detection circuit coupled to receive the boosting control signal and provide a boosted voltage signal having an oscillator enable state and an oscillator disable state;

a boosted potential node coupled to the word selection circuit, the boosted potential node providing charge to the activated word line;

an oscillation circuit coupled to generate an oscillation signal that has periodic logic transitions when the boosted voltage signal is in the oscillator enable state; and

a booster circuit coupled to provide charge to the boosted potential node in response to logic transitions in the oscillation signal.

15. The semiconductor memory device according to claim 14, wherein:

the boosting control circuit generates the boosting control signal that is a one-shot pulse; and

a command decoder is coupled to receive an externally applied command and generate the control signal.

16. The semiconductor memory device according to claim 14, wherein:

the boosted potential detection circuit includes a comparator that compares a reference potential and a boosted level indicating potential and generates the boosted voltage signal having an oscillator enable state when the reference potential is greater than the boosted level indicating potential.

17. The semiconductor memory device according to claim 14, wherein:

the boosting control circuit generates the boosting control signal having a first boosting control logic state when a word line is to be enabled; and

the boosted potential detection circuit generates the boosted voltage signal having the oscillator enable state when the boosting control signal has the first boosting control logic state.

18. The semiconductor memory device according to claim 14, wherein the oscillation circuit includes:

an oscillation signal generator having a ring oscillator coupled to generate the oscillation signal having periodic logic transitions determined by a propagation delay of the ring oscillator;

an oscillator preset circuit that presets the oscillation circuit to trigger a first logic transition in the oscillation signal when the boosted voltage signal transitions from the oscillator disable state to the oscillator enable state; and

the time from the boosted voltage signal transitioning from the oscillator disable state to the oscillator enable state to the first logic transition in the oscillation signal is less than the propagation delay of the ring oscillator.

19. The semiconductor memory device according to claim 18, wherein:

the oscillation circuit further includes a latch circuit for latching the state of the oscillation signal when the boosted voltage signal is in the oscillator disable state.

20. The semiconductor memory device according to claim 14, wherein the oscillation circuit includes:

a current source coupled to receive a reference potential and provide current from a power supply terminal to a ring oscillator; and

the time delay between periodic logic transitions of the oscillation signal is dependent upon the reference potential.