Programmable multi-tasking memory management system
First Claim
1. A method for performing multiple tasks simultaneously in a System On a Chip (SOC) device, comprising:
- processing system and application tasks using a first processor, the first processor being connected to a system bus and being adapted to receive system and applications requests from a plurality of communication cores; and
processing memory management tasks using a memory management system having a second processor while processing system and application tasks are being performed, the memory management system being connected to the system bus and to the plurality of communications cores through dedicated memory buses, wherein the second processor is adapted to perform at least one of memory routing and switching tasks among the plurality of communication cores.
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Abstract
A highly intelligent programmable multi-tasking memory management system manages memory requests associated with a system on chip (SOC) device. The memory management system includes a routing controller or central processing unit (RCPU) that is used for routing/switching stream data between communication cores and digital signal processors with minimum reliance and demand on a main or virtual central processing unit (VCPU) residing on a system bus. Tasks are partitioned between the VCPU and the RCPU within the SOC architecture for communication applications. The VCPU performs system/application tasks while the RCPU simultaneously performs multiple memory routing/switching tasks and multiple concurrent memory access connections. The memory management system also enables other processors and communication cores to update their internal data once new data is written in the memory system. In addition, a method and system are provided for performing predictive protocol fetch for multiple DSPs on the SOC to increase data processing throughput.
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Citations
17 Claims
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1. A method for performing multiple tasks simultaneously in a System On a Chip (SOC) device, comprising:
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processing system and application tasks using a first processor, the first processor being connected to a system bus and being adapted to receive system and applications requests from a plurality of communication cores; and
processing memory management tasks using a memory management system having a second processor while processing system and application tasks are being performed, the memory management system being connected to the system bus and to the plurality of communications cores through dedicated memory buses, wherein the second processor is adapted to perform at least one of memory routing and switching tasks among the plurality of communication cores. - View Dependent Claims (2, 3, 4, 5, 6, 7)
inputting memory requests from the plurality of communication cores to a request buffer;
outputting the memory requests from the request buffer to a foreground request schedule and a background request schedule;
queuing the memory requests in the foreground request schedule followed by queuing the memory requests in the background request schedule; and
processing simultaneously a predetermined number of memory requests.
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6. The method according to claim 5, wherein the predetermined number of memory requests corresponds to the number of memory controllers in the memory management system.
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7. The method according to claim 5, wherein the foreground requests correspond to requests residing in an SRAM buffer.
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8. A memory management system for routing or switching stream data among a plurality of peripheral masters on a System on a Chip (SOC) device, the system comprising:
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a multiplexer for selecting a predetermined number of peripheral memory requests from the plurality of peripheral masters;
a multi tasking arbiter and load balancing system coupled to the multiplexer and adapted to provide an arbitration, load balancing and scheduling scheme to the multiplexer;
a bus bridge for receiving a system request from a system master; and
a routing CPU coupled to the multiplexer and the bus bridge for processing both the peripheral memory requests and the system request. - View Dependent Claims (9)
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10. A System On a Chip (SOC) device comprising:
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a virtual master for processing system and application tasks requested by a plurality of peripheral masters, the plurality of peripheral masters adapted to transmit memory requests associated with one or more memory banks; and
a memory management system having a routing master for receiving and processing the memory requests from the plurality of peripheral masters. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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Specification