Method and apparatus for retiming in a network of multiple context processing elements

• US 6,526,498 B1
• Filed: 02/15/2000
• Issued: 02/25/2003
• Est. Priority Date: 10/31/1997
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Eslick, Ian, French, Robert, Mirsky, Ethan
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US09/504,203
• Time in Patent Office: 1,106 Days
• Field of Search: 712/10, 712/11, 712/14, 712/15, 712/16, 712/37, 712/18, 712/228, 365/185, 365/201, 365/900, 716/6, 716/16, 716/17, 709/108, 713/401
• US Class Current: 712/11
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus

Abstract

A method and an apparatus for retiming in a network of multiple context processing elements are provided. A programmable delay element is configured to programmably delay signals between a number of multiple context processing elements of an array without requiring a multiple context processing element to implement the delay. The output of a first multiple context processing element is coupled to a first multiplexer and to the input of a number of serially connected delay registers. The output of each of the serially connected delay registers is coupled to the input of a second multiplexer. The output of the second multiplexer is coupled to the input of the first multiplexer, and the output of the first multiplexer is coupled to a second multiple context processing element. The first and second multiplexers are provided with at least one set of data representative of at least one configuration memory context of a multiple context processing element. The first and second multiplexers are controlled to select one of a number of delay durations in response to the received set of data. A delay is programmed in the network structure in response to a data type being transferred between particular multiple context processing elements.

Claims

1. A method for retiming a networked array of multiple context processing elements, the method comprising programming a delay using at least one multiplexer and at least one clocked delay circuit in response to at least one configuration memory context of a multiple context processing element, the at least one multiplexer and the at least one clocked delay circuit coupled among a plurality of multiple context processing elements, the delay programmed with at least one set of data representative of the at least one configuration memory context.

2. The method of claim 1, wherein the at least one delay register comprises at least one latch.

3. The method of claim 1, wherein the programming further comprises programming the delay in response to data being transferred between multiple context processing elements.

4. The method of claim 1, further comprising:

coupling the output of a first multiple context processing element to a first multiplexer and to the input of a plurality of serially connected delay registers;

coupling the output of each of the plurality of serially connected delay registers to the input of a second multiplexer, the output of the second multiplexer coupled to the input of the first multiplexer; and

coupling the output of the first multiplexer to a second multiple context processing element.

5. The method of claim 4, wherein the programming comprises:

providing the first and second multiplexers with at least one set of data representative of at least one configuration memory context of a multiple context processing element;

controlling the first and second multiplexers to select one of a plurality of delay durations in response to the at least one set of data.

7. The method of claim 1, wherein the programmed delay is implemented among the plurality of multiple context processing elements without having a multiple context processing element implement the delay.

8. The method of claim 1, the multiple context processing element comprising:

a memory,

an arithmetic logic unit,

control logic, and

a network port,

wherein the network port connects the memory, arithmetic logic unit, and control logic to the networked array of multiple context processing elements.

6. A method for retiming a networked array of multiple context processing elements, comprising:

programming a delay using at least one multiplexer and at least one clocked delay circuit in response to at least one configuration memory context of a multiple context processing element, the at least one multiplexer and the at least one clocked delay circuit coupled among a plurality of multiple context processing elements, the delay programmed with at least one set of data representative of the at least one configuration memory context;

assigning virtual identifications to a plurality of multiple context processing elements;

transmitting data to at least one of the plurality of multiple context processing elements, the data comprising an address mask;

comparing the virtual identification of each of the plurality of multiple context processing elements masked with the address mask to a masked destination identification; and

when the masked virtual identification of a multiple context processing element matches the masked destination identification, manipulating at least one of the plurality of multiple context processing elements in response to the transmitted data, the manipulated multiple context processing elements defining at least one region of the networked array.

9. An apparatus for providing retiming in a networked array of multiple context processing elements, the apparatus comprising:

at least one clocked delay circuit coupled among multiple context processing elements; and

at least one multiplexer coupled to the at least one clocked delay circuit, the at least one multiplexer selecting a delay duration in response to at least one configuration memory context of a multiple context processing element, the delay programmed in response to a data type being transferred among multiple context processing elements.

10. The apparatus of claim 9, wherein the at least one delay register comprises at least one latch.

11. The apparatus of claim 9, wherein:

an output of a first multiple context processing element is coupled to a first multiplexer and to the input of a plurality of serially connected delay registers;

an output of each of the plurality of serially connected delay registers is coupled to the input of a second multiplexer, the output of the second multiplexer coupled to the input of the first multiplexer; and

an output of the first multiplexer is coupled to a second multiple context processing element.

12. The apparatus of claim 11, wherein:

the first and second multiplexers are provided with at least one set of data representative of at least one configuration memory context of a multiple context processing element;

the first and second multiplexers are controlled to select one of a plurality of delay durations in response to the at least one set of data.

13. The apparatus of claim 9, wherein the programmed delay is implemented among the networked array of multiple context processing elements without having a multiple context processing element implement the delay.

14. The apparatus of claim 9, the multiple context processing element comprising:

a memory,

an arithmetic logic unit,

control logic, and

a network port,

wherein the network port connects the memory, arithmetic logic unit, and control logic to the networked array of multiple context processing elements.

15. A method for retiming a networked array of multiple context processing elements, the method comprising using a programmable clocked delay element configured to programmably delay signals among a plurality of multiple context processing elements without requiring a multiple context processing element to implement the delay, the delay programmed with at least one set of data representative of at least one configuration memory context.

16. The method of claim 15, further comprising programming a delay using at least one multiplexer and at least one delay register in response to at least one configuration memory context of a multiple context processing element, the at least one multiplexer and the at least one delay register coupled between a plurality of multiple context processing elements.

17. The method of claim 16, wherein the programming comprises:

providing the first and second multiplexers with at least one set of data representative of at least one configuration memory context of a multiple context processing element;

controlling the first and second multiplexers to select one of a plurality of delay durations in response to the at least one set of data.

18. The method of claim 17, further comprising:

coupling at least one delay register and at least one multiplexer between a plurality of multiple context processing elements of the array; and

programming a delay using the at least one multiplexer in response to at least one configuration memory context of a multiple context processing element.

19. The method of claim 15, the multiple context processing element comprising:

a memory,

an arithmetic logic unit,

control logic, and

a network port,

wherein the network port connects the memory, arithmetic logic unit, and control logic to the networked array of multiple context processing elements.

20. An apparatus for providing retiming in a networked array of multiple context processing elements, the apparatus comprising a programmable clocked delay element configured to programmably delay signals among a plurality of multiple context processing elements without requiring a multiple context processing element to implement the delay, the delay signals programmed in response to a data type being transferred among the plurality of multiple context processing elements.

21. The apparatus of claim 20, the multiple context processing element comprising:

a memory,

an arithmetic logic unit,

control logic, and

a network port,

wherein the network port connects the memory, arithmetic logic unit, and control logic to the networked array of multiple context processing elements.