Method for improving area in reduced programmable logic devices
First Claim
1. A method for creating a reduced logic block model from a configurable logic block model, the method comprising:
- defining wired paths in place of a plurality of configured selector circuits in the configurable logic block model;
defining a non-configurable logic circuit in place of configured function generators of the configurable logic block model.
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Abstract
Method and circuits to create reduced field programmable gate arrays (RFPGA) from the configuration data of field programmable gate arrays (FPGA) are disclosed. The configurable elements of the FPGA are replaced with standard cell circuits that reproduce the functionality of the configured FPGA. Specifically, reduced logic blocks are derived from the configuration data of configurable logic blocks. Similarly, reduced input/output blocks and reduced matrices are derived from the configuration data for input/output blocks and programmable switch matrices of the FPGA, respectively. The reduced logic blocks are arranged in a similar layout to the original CLBs so that timing relationships remain similar in the RFPGA and FPGA. The actual timing of the RFPGA can be modified by increasing or decreasing the timing delay on various signal paths based on the FPGA design or additional timing constraints. To reduce the time required to generate RFPGAs, a database can be used to contain configurable logic block models and the corresponding reduced logic block models. The database can be expanded as new reduced logic block models are created for configurable logic block models that were not in the database. Similarly, a database can be used for the input/output blocks and programmable switch matrices of an FPGA.
90 Citations
37 Claims
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1. A method for creating a reduced logic block model from a configurable logic block model, the method comprising:
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defining wired paths in place of a plurality of configured selector circuits in the configurable logic block model;
defining a non-configurable logic circuit in place of configured function generators of the configurable logic block model. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for creating a reduced input/output block model from a configurable input/output block model, the method comprising:
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defining wired paths in place of a plurality of configured selector circuits in the configurable input/output block model;
defining a non-configurable logic circuit in place of configured circuits of the configurable input/output block model. - View Dependent Claims (13, 14, 15, 16)
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17. A method for creating a reduced matrix model from a programmable switch matrix model having a plurality of programmable interconnect points, wherein each programmable interconnect point can be configured to interconnect a plurality of wires, the method comprising:
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determining the configuration of each programmable interconnect point;
defining a set of one or more wired paths in place of each programmable interconnect point configured to interconnect any of said wires to create a plurality of sets of wired paths; and
removing unused programmable interconnect points. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25)
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26. A method for creating a reduced logic block model from a configurable logic block model, the method comprising the steps of:
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extracting configuration data for input/output blocks (IOBs), configurable logic blocks (CLBs), and programmable switch interconnect including programmable switch matrices (PSMs);
generating IOB and CLB models;
estimating an area required for reduced input/output blocks (RIOBs), reduced logic blocks (RLBs), reduced interconnect, and reduced matrices (RMs) by approximating an area for each RIOB, RLB, and reduced interconnect;
building a routing grid for RLBs inside a routing ring and a routing grid for RIOBs outside the routing ring building RLB and RIOB models using the IOB and CLB models generated and the area estimated for the RIOBs, RLBS, and reduced interconnect;
deriving a draw list for the reduced interconnect;
interconnecting RLBs using a route reduced interconnect;
building the routing ring;
routing connections between RLB and the routing ring;
and placing the RIOBs around the routing ring. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37)
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Specification