Chip scale surface-mountable packaging method for electronic and MEMS devices

• US 6,528,344 B2
• Filed: 06/22/2001
• Issued: 03/04/2003
• Est. Priority Date: 06/22/2000
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, Seok-jin
• Primary Examiner(s): Cuneo, Kamand
• Assistant Examiner(s): GEYER, SCOTT B
• Application Number:
  US09/886,286
• Publication Number:
  US 20020001873A1
• Time in Patent Office: 620 Days
• Field of Search: 438/113, 438/106, 438/107, 438/110, 438/118, 438/121, 438/125, 438/455, 438/456, 438/459
• US Class Current: 438/106
• CPC Class Codes: B81B 7/0077 Other packages not provided for in groups B81B7/0035 - B81B7/0074
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A chip scale surface-mountable packaging method for electronic and micro-electro mechanical system (MEMS) devices is provided. The chip scale surface-mountable packaging method includes: (a) forming an interconnection and sealing pattern as a deep trench in one surface of a conductive cover substrate using semiconductor fabricating and micromachining techniques; (b) filling the trench as the pattern of the cover substrate with an insulating material such as glass or ceramic, and planarizing the surface of the cover to form a bonding pattern; (c) accurately aligning the cover substrate with a device substrate, in which electronic or MEMS devices are integrated, and bonding the cover substrate and the device substrate; (d) polishing the other surface of the cover substrate and forming an electrode pattern thereon; and (e) dicing the sealed and interconnected substrates to form a complete chip scale package. Thus, both sealing of the electronic or MEMS devices and their interconnection with external devices can be achieved at a wafer level.

Claims

1. A chip scale surface-mountable packaging method for electronic and micro-electro mechanical system (MEMS) devices, comprising:

(a) forming an interconnection and sealing pattern as a trench in one surface of a conductive cover substrate using semiconductor fabricating and micromachining techniques;

(b) filling the trench as the pattern of the cover substrate with an insulating material selected from the group consisting of glass and ceramic, and planarizing the surface of the cover substrate having the insulating material to form a bonding pattern;

(c) aligning the cover substrate with a device substrate, in which electronic or MEMS devices are integrated, and bonding the cover substrate and the device substrate; and

(d) polishing the other surface of the cover substrate and forming an electrode pattern thereon.

2. The method of claim 1, wherein the cover substrate is formed as an impurity-doped conductive semiconductor substrate or a metal substrate.

3. The method of claim 2, wherein the semiconductor substrate is formed of silicon (Si), and the metal substrate is formed of a metal selected from the group consisting of stainless steel, Kovar, and copper (Cu).

4. The method of claim 2, wherein, in step (a) of forming the interconnection and sealing pattern in the cover substrate, the trench has a depth of more than two hundred and less than a thousand micrometers.

5. The method of claim 1, wherein, in filling the trench of the cover substrate with ceramic in step (b), ceramic paste is coated on the surface of the cover substrate and packed into the trench of the cover substrate, and the resultant cover substrate is thermally processed in a furnace.

6. The method of claim 1, wherein planarizing the cover substrate in step (b) is performed using chemical mechanical polishing (CMP) to minimize surface roughness of the cover substrate and to expose the interconnection and bonding patterns.

7. The method of claim 1, wherein, in filling the trench of the cover substrate having the interconnection and sealing pattern with glass in step (b), the cover substrate is bonded with a glass substrate in a vacuum and the resultant bonded substrates are processed in a furnace.

8. The method of claim 1, wherein step (c) is performed by a bonding method selected from the group consisting of solder bonding, eutectic bonding, zero gap bonding, anisotropic conductive film bonding, conductive epoxy bonding, and anodic bonding.

9. The method of claim 1, further comprising:

dicing the sealed and interconnected substrates to form a complete chip scale package.

10. The method of claim 1, wherein the trench is formed outside a cavity for containing electronic or MEMS devices.