Method for fabricating a trench MOS power transistor

• US 6,528,355 B2
• Filed: 01/28/2002
• Issued: 03/04/2003
• Est. Priority Date: 07/28/1999
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Hirler, Franz, Kotek, Manfred, Larik, Joost
• Primary Examiner(s): Nguyen, Tuan H.
• Application Number:
  US10/058,526
• Publication Number:
  US 20020094635A1
• Time in Patent Office: 400 Days
• Field of Search: 438/133, 438/135, 438/136, 438/137, 438/138, 438/173, 438/212, 438/268, 438/270
• US Class Current: 438/135
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for fabricating a trench MOS transistor includes the step of at least partly filling the trench with a conductive material which is isolated from the inner surface of the trench by an insulating layer. The insulating layer has a layer thickness that is larger in the region of the lower end of the trench than at the upper end of the trench.

Claims

1. A method for fabricating a trench MOS power transistor, the method which comprises:

forming a trench in a semiconductor body;

coating walls and a bottom of the trench with a first insulating film of a given final thickness by applying the first insulating film as a plurality of thermally oxidized and deposited layers;

filling a lower end of the trench with an auxiliary layer;

removing the first insulating film in regions not coated with the auxiliary layer;

removing the auxiliary layer;

growing a second insulating film on uncovered walls at an upper end of the trench such that the second insulating film is thinner than the given final thickness of the first insulating film;

filling the trench at least partly with a conductive material such that the conductive material is insulated from an inner surface of the trench by the first insulating layer and the second insulating layer; and

introducing source zones and body zones into the semiconductor body and providing metallization layers for providing contacting connections.

2. The method according to claim 1, which comprises forming the trench in an epitaxial layer provided on a semiconductor substrate.

3. The method according to claim 2, which comprises providing the epitaxial layer with a dopant concentration of 1×

10¹⁴ to 1×

10¹⁸ charge carriers cm<sup>−

3</sup>.

4. The method according to claim 1, which comprises forming trenches in the semiconductor body such that the trenches are one of strip-shaped and lattice-shaped.

5. The method according to claim 1, which comprises applying the first insulating film with a layer thickness of substantially 0.1 μ

m to several μ

m.

6. The method according to claim 1, which comprises using a photoresist as the auxiliary layer.

7. The method according to claim 1, which comprises applying a further auxiliary layer as an additional masking for an edge construction such that the further auxiliary layer prevents a removal of the first insulating film in masked regions.

8. The method according to claim 1, which comprises applying the second insulating film with a layer thickness of a few nm to in excess of 100 nm.

9. The method according to claim 1, which comprises introducing a reinforcement into a body region.

10. The method according to claim 9, which comprises implanting the reinforcement.

11. The method according to claim 1, which comprises, subsequent to coating the walls and the bottom of the trench with the first insulating film, applying a silicon nitride layer on the first insulating film and patterning the silicon nitride layer.

12. The method according to claim 11, which comprises providing the silicon nitride layer with a layer thickness of substantially 20 nm.

13. The method according to claim 1, which comprises patterning the auxiliary layer and the first insulating film by using a single photoresist layer and a mask and by exposing the single photoresist layer only down to a given depth.

14. The method according to claim 1, which comprises covering inactive trenches by introducing a first photoresist layer into the inactive trenches and patterning the first insulating film by using a second photoresist layer applied outside the first photoresist layer.

15. The method according to claim 14, which comprises applying the second photoresist layer subsequent to applying the first photoresist layer.