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Method for fabricating a trench MOS power transistor

  • US 6,528,355 B2
  • Filed: 01/28/2002
  • Issued: 03/04/2003
  • Est. Priority Date: 07/28/1999
  • Status: Active Grant
First Claim
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1. A method for fabricating a trench MOS power transistor, the method which comprises:

  • forming a trench in a semiconductor body;

    coating walls and a bottom of the trench with a first insulating film of a given final thickness by applying the first insulating film as a plurality of thermally oxidized and deposited layers;

    filling a lower end of the trench with an auxiliary layer;

    removing the first insulating film in regions not coated with the auxiliary layer;

    removing the auxiliary layer;

    growing a second insulating film on uncovered walls at an upper end of the trench such that the second insulating film is thinner than the given final thickness of the first insulating film;

    filling the trench at least partly with a conductive material such that the conductive material is insulated from an inner surface of the trench by the first insulating layer and the second insulating layer; and

    introducing source zones and body zones into the semiconductor body and providing metallization layers for providing contacting connections.

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