Manufacture of semiconductor capacitively-coupled NDR device for applications such as high-density high-speed memories and power switches

• US 6,528,356 B2
• Filed: 03/20/2002
• Issued: 03/04/2003
• Est. Priority Date: 06/05/1998
• Status: Expired due to Fees

• Current Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford Management Co.)
• Original Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford Management Co.)
• Inventors: Nemati, Farid, Plummer, James D.
• Primary Examiner(s): Ho, Hoai
• Assistant Examiner(s): HOANG, QUOC DINH
• Application Number:
  US10/103,240
• Publication Number:
  US 20020096690A1
• Time in Patent Office: 349 Days
• Field of Search: 438/133, 438/135, 438/138, 438/241, 438/268
• US Class Current: 438/135
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1027 Thyristors
• CPC Class Codes: H01L 29/41716 Cathode or anode electrodes for thyristors
• CPC Class Codes: H01L 29/42308 Gate electrodes for thyristors
• CPC Class Codes: H01L 29/74 Thyristor-type devices, e.g. having four-zone regenerative action two-terminal thyristors H01L29/87
• CPC Class Codes: H01L 29/749 with turn-on by field effect
• CPC Class Codes: H01L 29/87 Thyristor diodes, e.g. Shockley diodes, break-over diodes
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 12/10 DRAM devices comprising bipolar components

Abstract

A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure with capacitively-coupled gate-assisted turn-off and turn-on mechanisms. An SRAM based on this new device is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. In one embodiment, an NDR-based SRAM cell consists of only two elements, has an 8 F² footprint, can operate at high speeds and low voltages, has a good noise-margin, and is compatible in fabrication process with main-stream CMOS. This cell significantly reduces standby power consumption compared to other types of NDR-based SRAMs.

Claims

1. A method for manufacturing a semiconductor device having a thyristor device with NDR characteristics, the method comprising:

forming at least two contiguous regions of the thyristor device, said at least two contiguous regions being of opposite polarity;

forming a control port that is located adjacent to, capacitively coupled to, and facing at least one of the regions of the thyristor device, the thyristor device including the control port and said at least two contiguous regions, the control port and said at least two contiguous regions being formed to provide at least preponderant control for switching of the thyristor device from a current-passing mode to a current-blocking mode in response to the control port coupling at least one edge of a first voltage pulse to said at least one of the regions, and from a current-blocking mode to a current-passing mode in response to the control port coupling at least one edge of a second voltage pulse to said at least one of the regions, each of the first and second voltage pulses having a common polarity.

2. A method for manufacturing a semiconductor device, according to claim 1, further including forming at least one other thyristor device that also has at least two contiguous regions of opposite polarity and a control port located adjacent to and facing at least one of the regions of the one other thyristor device.

3. A method for manufacturing a semiconductor device, according to claim 2, further including forming a semiconductor power switch that includes the thyristor devices.

4. A method for manufacturing a semiconductor device, the method comprising:

forming memory cells in an array, each of the memory cells having a thyristor device with NDR characteristics;

for each thyristor device,

forming at least two contiguous regions of the thyristor device, said at least two contiguous regions being of opposite polarity, and

forming a control port that is located adjacent to, capacitively coupled to, and facing at least one of the regions of the thyristor device, the thyristor device including the control port and said at least two contiguous regions, the control port and the thyristor device being formed to enhance switching of the thyristor device from a current-passing mode to a current-blocking mode in response to the control port coupling at least one edge of a first voltage pulse to said at least one of the regions, and from a current-blocking mode to a current-passing mode in response to the control port coupling at least one edge of a second voltage pulse to said at least one of the regions, each of the first and second voltage pulses having a common polarity.

5. A method for manufacturing a semiconductor device, according to claim 4, wherein each of memory cells includes a storage node and a control circuit configured and arranged to provide access to the storage node, and wherein the control port of the thyristor device is formed to enhance writing access to the storage node.

6. A method for manufacturing a semiconductor device, the method comprising:

forming a thyristor device with NDR characteristics that has at least two contiguous regions of opposite polarity and has a control port that is located adjacent to, capacitively coupled to, and facing at least one of the regions of the thyristor device;

the control port and the thyristor device being formed to enhance switching of the thyristor device from a current-passing mode to a current-blocking mode in response to the control port coupling at least one edge of a first voltage pulse to said at least one of the regions, and from a current-blocking mode to a current-passing mode in response to the control port coupling at least one edge of a second voltage pulse to said at least one of the regions, each of the first and second voltage pulses having a common polarity; and

forming a layer of insulative material as part of a silicon-on-insulator structure, wherein the thyristor device is located adjacent the insulative material.

7. A method for manufacturing a semiconductor device, according to claim 6, further including forming a semiconductor power switch, wherein the control port and the thyristor device are formed as part of the semiconductor power switch.

8. A method for manufacturing a semiconductor device, according to claim 6, further including forming a memory cell with the control port and the thyristor device being formed as components in the memory cell.

9. A method for manufacturing a semiconductor device, the method comprising:

forming a memory cell having a thyristor device with NDR characteristics;

the thyristor device being formed to include at least two contiguous regions of opposite polarity and a control port that is located adjacent to, capacitively coupled to, and facing at least one of the regions of the thyristor device;

the control port and the thyristor device being formed to enhance switching of the thyristor device from a current-passing mode to a current-blocking mode in response to the control port coupling at least one edge of a first voltage pulse to said at least one of the regions, and from a current-blocking mode to a current-passing mode in response to the control port coupling at least one edge of a second voltage pulse to said at least one of the regions, each of the first and second voltage pulses having a common polarity, and wherein the control port is formed in the semiconductor device to respond to a word line and the thyristor device is adapted to provide two stable states for the memory cell.

10. A method for manufacturing a semiconductor device, according to claim 9, wherein the control port and the thyristor device are formed to enhance switching of the thyristor device from a current-passing mode to a current-blocking mode by responding to the control port coupling both leading and trailing edges of a pulse carried by the word line to said at least one of the regions.

11. A method for manufacturing a semiconductor device, according to claim 9, wherein the control port and the thyristor device are formed to enhance switching of the thyristor device from a current-passing mode to a current-blocking mode by responding to the control port coupling both leading and trailing edges of the first voltage pulse to said at least one of the regions.

12. A method for manufacturing a semiconductor device, according to claim 9, wherein the contiguous regions of opposite polarity are vertically arranged.

13. A method for manufacturing a semiconductor device, according to claim 9, wherein the control port and said at least two contiguous regions are formed to provide switching of the thyristor device between a current-passing mode and a current-blocking mode independent of any insulated-gate field-effect transistor inversion channel formation against said at least one of the regions.

14. A method for manufacturing a semiconductor memory device, the method comprising:

forming a thyristor device with NDR characteristics and having at least two contiguous regions of opposite polarity and a control port that is located adjacent to, capacitively coupled to, and facing at least one of the regions of the thyristor device;

the control port and the thyristor device being formed to enhance switching of the thyristor device from a current-passing mode to a current-blocking mode in response to the control port coupling at least one edge of a first voltage pulse to said at least one of the regions, and from a current-blocking mode to a current-passing mode in response to the control port coupling at least one edge of a second voltage pulse to said at least one of the regions, each of the first and second voltage pulses having a common polarity; and

forming an SRAM device having a storage node, a bit line, a first word line, a second word line, an access circuit having a control port connected to the first word line and formed to provide read and write access between the storage node and the bit line.

15. A method for manufacturing a semiconductor memory device, according to claim 14, further comprising forming a standby circuit to provide a standby current for the thyristor device.

16. A method for manufacturing a semiconductor memory device, according to claim 14, wherein the thyristor device and the second word line are arranged vertically.

17. A method for manufacturing a semiconductor memory device, according to claim 14, wherein the thyristor device, the second word line, the access circuit and the first word line are arranged vertically.

18. A method for manufacturing a semiconductor memory device, according to claim 14, wherein the control port and said at least two contiguous regions are formed to provide switching of the thyristor device between a current-passing mode and a current-blocking mode independent of any insulated-gate field-effect transistor inversion channel formation against said at least one of the regions.

19. A method for manufacturing a semiconductor device having a thyristor device with NDR characteristics, the method comprising:

forming at least two contiguous regions of the thyristor device, said at least two contiguous regions being of opposite polarity;

forming a control port that is located adjacent to, capacitively coupled to, and facing at least one of the regions of the thyristor device, the thyristor device including the control port and said at least two contiguous regions, the control port and said at least two contiguous regions being formed to provide switching of the thyristor device between a current-passing mode and a current-blocking mode in response to the control port coupling at least part of a voltage pulse to said at least one of the regions and independent of any insulated-gate field-effect transistor inversion channel formation against said at least one of the regions.

20. A method for manufacturing a semiconductor memory device, according to claim 19, wherein the control port and said at least two contiguous regions being formed to provide at least preponderant control for switching of the thyristor device between a current-passing mode and a current-blocking mode in response to the control port coupling at least part of a voltage pulse to said at least one of the regions.