Protection of tungsten alignment mark for FeRAM processing

• US 6,528,386 B1
• Filed: 03/13/2002
• Issued: 03/04/2003
• Est. Priority Date: 12/20/2001
• Status: Expired due to Term

• Current Assignee: Broadcom International Pte Ltd. (Broadcom, Inc.), Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Aggarwal, Sanjeev, Summerfelt, Scott R., Colombo, Luigi, Moise, Theodore S. IV, Gilbert, Stephen R.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Dang, Phuc T.
• Application Number:
  US10/097,919
• Time in Patent Office: 356 Days
• Field of Search: 438/401, 438/637, 438/648, 438/677, 438/692, 438/700, 438/975, 438/633, 438/643, 438/703
• US Class Current: 438/401
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: H10B 53/30 characterised by the memory core region

Abstract

A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the patterning of a top electrode layer and a dielectric layer to form a capacitor stack structure having sidewalls associated therewith. Prior to patterning the bottom electrode layer, a protective film is formed on the sidewalls of the capacitor stack structure in order to protect the dielectric material from conductive contaminants associated with a subsequent patterning of the bottom electrode layer.

Claims

1. A method of forming an FeRAM capacitor over one or more transistors associated with a semiconductor substrate, comprising:

forming a dielectric layer over the one or more transistors;

forming a contact via and an alignment mark via in the dielectric layer, wherein the contact via extends down to a portion of one of the one or more transistors;

forming a tungsten layer over the dielectric layer, wherein the tungsten layer fills the contact via and is substantially conformal with respect to the alignment mark via, wherein a sidewall surface of a portion of the tungsten layer within the alignment mark via has a roughness associated therewith;

reducing the sidewall surface roughness of the tungsten layer within the alignment mark via;

patterning the tungsten layer, thereby electrically isolating the contact via and the alignment mark via, respectively;

forming capacitor stack layers over the dielectric layer, the contact via and the alignment mark via, respectively, wherein the capacitor stack layers are substantially conformal with respect to the alignment mark via thereunder, thereby resulting in a topology variation in a top portion of the capacitor stack layers associated with the alignment mark via;

using the topology difference in the capacitor stack layers as an alignment mark to position a patterned hard mask over the capacitor stack layers; and

patterning the capacitor stack layers using the patterned hard mask, thereby defining a capacitor stack structure.

2. The method of claim 1, wherein forming the capacitor stack layers further comprises:

forming a barrier layer over the dielectric layer, wherein the barrier layer covers both the dielectric layer and the patterned tungsten layer in the contact via and the alignment mark via, respectively;

forming a bottom electrode layer over the barrier layer;

forming a ferroelectric dielectric layer over the bottom electrode layer; and

forming a top electrode layer over the ferroelectric dielectric layer.

3. A method of forming an FeRAM capacitor over one or more transistors associated with a semiconductor substrate, comprising:

forming a dielectric layer over the one or more transistors;

forming a contact via and an alignment mark via in the dielectric layer, wherein the contact via extends down to a portion of one of the one or more transistors;

forming a tungsten layer over the dielectric layer, wherein the tungsten layer fills the contact via and is substantially conformal with respect to the alignment mark via, wherein a sidewall surface of a portion of the tungsten layer within the alignment mark via has a roughness associated therewith;

reducing the sidewall surface roughness of the tungsten layer within the alignment mark via, wherein reducing the sidewall surface roughness of the tungsten layer within the alignment mark via comprises;

forming a smoothing layer over the tungsten layer; and

patterning the smoothing layer, wherein the patterning removes the smoothing layer on a portion of the tungsten layer which overlies the dielectric layer and the contact via, and leaves another portion of the smoothing layer on the sidewall surface of the tungsten layer within the alignment mark via;

patterning the tungsten layer, thereby electrically isolating the contact via and the alignment mark via, respectively;

forming capacitor stack layers over the dielectric layer, the contact via and the alignment mark via, respectively, wherein the capacitor stack layers are substantially conformal with respect to the alignment mark via thereunder, thereby resulting in a topology variation in a top portion of the capacitor stack layers associated with the alignment mark via;

using the topology difference in the capacitor stack layers as an alignment mark to position a patterned hard mask over the capacitor stack layers; and

patterning the capacitor stack layers using the patterned hard mask, thereby defining a capacitor stack structure.

4. The method of claim 3, wherein patterning the smoothing layer comprises performing a chemical mechanical polish, thereby removing the smoothing layer and the tungsten layer at a region overlying the dielectric layer and the contact via.

5. The method of claim 3, wherein patterning the smoothing layer comprises performing a chemical etch thereof.

6. The method of claim 5, further comprising forming a barrier layer over the tungsten layer before forming the smoothing layer, wherein the barrier layer serves as an etch stop during the chemical etch of the smoothing layer.

7. The method of claim 6, wherein the barrier layer comprises TiN, TiAlN, TaSiN, ZrN or HfN.

8. The method of claim 6, further comprising cleaning the tungsten layer prior to forming the barrier layer.

9. The method of claim 8, wherein cleaning the tungsten layer comprises:

performing an Ar plasma clean; and

preventing an exposure of the cleaned tungsten layer to air between the cleaning and the formation of the barrier layer.

10. The method of claim 3, wherein the smoothing layer comprises SiO2, and wherein patterning the SiO₂ smoothing layer comprises performing a chemical etch with a fluorine containing etch chemistry.

11. The method of claim 10, further comprising adding oxygen to the fluorine containing etch chemistry.

12. The method of claim 6, further comprising etching the barrier layer after an etching of the smoothing layer, thereby removing a portion of the barrier layer over the dielectric layer and the contact via, and leaving another portion of the sidewall surface of the alignment mark via.

13. The method of claim 3, wherein the smoothing layer comprises SiO₂, Si₃N₄, SiN, AlOx, TaOx, or TiO₂.

14. The method of claim 3, wherein forming the smoothing layer comprises depositing a SiO₂ layer using chemical vapor deposition.

15. The method of claim 3, further comprising forming a barrier layer over the smoothing layer.

16. The method of claim 3, wherein forming the smoothing layer comprises:

forming a TiN, TiAlN, TaSiN, ZrN or HfN barrier layer over the tungsten layer in a substantially conformal manner using chemical vapor deposition;

forming an SiO₂, Si₃N₄ or SiN layer over the barrier layer in a substantially conformal manner using chemical vapor deposition; and

etching the smoothing layer with a fluorine containing etch chemistry, wherein the barrier layer serves as an etch stop, and wherein the etching removes the SiO₂, Si₃N₄ or SiN smoothing layer in regions overlying the dielectric layer and the contact via, and leaves a portion of the smoothing layer on the sidewall surface of the alignment mark via.

17. A method of forming an FeRAM capacitor over one or more transistors associated with a semiconductor substrate, comprising:

forming a dielectric layer over the one or more transistors;

forming a contact via and an alignment mark via in the dielectric layer, wherein the contact via extends down to a portion of one of the one or more transistors;

forming a tungsten layer over the dielectric layer, wherein the tungsten layer fills the contact via and is substantially conformal with respect to the alignment mark via, wherein a sidewall surface of a portion of the tungsten layer within the alignment mark via has a roughness associated therewith;

reducing the sidewall surface roughness of the tungsten layer within the alignment mark via, wherein reducing the sidewall surface roughness of the tungsten layer within the alignment mark via comprises removing a portion of the tungsten layer within the alignment mark via;

patterning the tungsten layer, thereby electrically isolating the contact via and the alignment mark via, respectively;

forming capacitor stack layers over the dielectric layer, the contact via and the alignment mark via, respectively, wherein the capacitor stack layers are substantially conformal with respect to the alignment mark via thereunder, thereby resulting in a topology variation in a top portion of the capacitor stack layers associated with the alignment mark via;

using the topology difference in the capacitor stack layers as an alignment mark to position a patterned hard mask over the capacitor stack layers; and

patterning the capacitor stack layers using the patterned hard mask, thereby defining a capacitor stack structure.

18. The method of claim 17, wherein the portion of the tungsten layer removed within the alignment mark via comprises substantially all of the tungsten layer within the alignment mark via.

19. The method of claim 18, wherein removing substantially all of the tungsten layer within the alignment mark via comprises:

forming a photoresist layer over the tungsten layer;

patterning the photoresist layer, thereby defining an opening over a portion of the tungsten layer within the alignment mark via; and

etching the tungsten layer through the opening.

20. The method of claim 17, wherein removing the portion of the tungsten layer comprises:

etching the tungsten film, wherein the etching reduces a surface roughness of the tungsten film including the sidewall surface roughness within the alignment mark via; and

performing a chemical mechanical polish of a remaining portion of the tungsten layer overlying the dielectric layer and the contact via.

21. The method of claim 20, further comprising etching with an Ar additive, wherein the Ar additive facilitates portions or removed tungsten to redeposit on the sidewall surface of the tungsten layer within the alignment mark via, thereby reducing the sidewall surface roughness associated therewith.

22. A method of forming an FeRAM capacitor over one or more transistors associated with a semiconductor substrate, comprising:

forming a dielectric layer over the one or more transistors;

forming a contact via and an alignment mark via in the dielectric layer, wherein the contact via extends down to a portion of one of the one or more transistors;

forming a tungsten layer over the dielectric layer, wherein the tungsten layer fills the contact via and is substantially conformal with respect to the alignment mark via, wherein a sidewall surface of a portion of the tungsten layer within the alignment mark via has a roughness associated therewith;

removing substantially all of the tungsten within the alignment mark via;

planarizing a portion of the tungsten layer overlying the dielectric layer, thereby electrically isolating the contact via and the alignment mark via, respectively;

forming capacitor stack layers over the dielectric layer, the contact via and the alignment mark via, respectively, wherein the capacitor stack layers are substantially conformal with respect to the alignment mark via thereunder, thereby resulting in a topology variation in a top portion of the capacitor stack layers associated with the alignment mark via;

using the topology difference in the capacitor stack layers as an alignment mark to position a patterned hard mask over the capacitor stack layers; and

patterning the capacitor stack layers using the patterned hard mask, thereby defining a capacitor stack structure.

23. A method of forming an FeRAM capacitor over one or more transistors associated with a semiconductor substrate, comprising:

forming a dielectric layer over the one or more transistors;

forming a contact via and an alignment mark via in the dielectric layer, wherein the contact via extends down to a portion of one of the one or more transistors;

forming a tungsten layer over the dielectric layer, wherein the tungsten layer fills the contact via and is substantially conformal with respect to the alignment mark via, wherein a sidewall surface of a portion of the tungsten layer within the alignment mark via has a roughness associated therewith;

removing substantially all of the tungsten within the alignment mark via, wherein removing substantially all of the tungsten layer within the alignment mark via comprises;

forming a photoresist layer over the tungsten layer;

patterning the photoresist layer, thereby defining an opening over a portion of the tungsten layer corresponding to the alignment mark via; and

etching the tungsten layer through the opening;

planarizing a portion of the tungsten layer overlying the dielectric layer, thereby electrically isolating the contact via and the alignment mark via, respectively;

forming capacitor stack layers over the dielectric layer, the contact via and the alignment mark via, respectively, wherein the capacitor stack layers are substantially conformal with respect to the alignment mark via thereunder, thereby resulting in a topology variation in a top portion of the capacitor stack layers associated with the alignment mark via;

using the topology difference in the capacitor stack layers as an alignment mark to position a patterned hard mask over the capacitor stack layers; and

patterning the capacitor stack layers using the patterned hard mask, thereby defining a capacitor stack structure.