High dielectric constant metal oxide gate dielectrics

• US 6,528,856 B1
• Filed: 12/15/1998
• Issued: 03/04/2003
• Est. Priority Date: 12/15/1998
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Doyle, Brian S., Bai, Gang, Cheng, Peng, Liang, Chunlin, Fraser, David B.
• Primary Examiner(s): ECKERT II, GEORGE C
• Application Number:
  US09/212,773
• Time in Patent Office: 1,540 Days
• Field of Search: 257/310, 257/405, 257/410, 257/411, 438/216, 438/287, 438/591
• US Class Current: 257/411
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/28229 by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence

Abstract

A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.

Claims

1. A field effect transistor (FET) comprising:

a metal oxide gate insulator disposed over a substantially intrinsic layer of silicon on a silicon substrate.

2. The FET of claim 1, wherein the metal oxide comprises an oxide of hafnium.

3. The FET of claim 1, wherein the metal oxide comprises an oxide of zirconium.

4. The FET of claim 1, wherein the metal oxide is an oxide of a rare earth element that has a higher heat of formation than silicon dioxide.

5. The FET of claim 1, wherein the substantially intrinsic layer of silicon is an epitaxial layer.

6. The FET of claim 1, further comprising a gate electrode overlying the metal oxide layer;

and source/drain terminals disposed in the substrate substantially adjacent the gate electrode.

7. The FET of claim 5, wherein the epitaxial layer has a thickness in the range of approximately 10 angstroms to 20 angstroms.

8. A field effect transistor (FET) comprising:

a metal oxide gate insulator disposed over a substantially intrinsic layer of silicon which overlies a silicon substrate, wherein the substantially intrinsic layer of silicon is an epitaxial layer

9. The FET of claim 8, wherein the epitaxial layer has a thickness in the range of approximately 10 angstroms to 20 angstroms.

10. The FET of claim 8, wherein the metal oxide comprises an oxide of hafnium.

11. The FET of claim 8, wherein the metal oxide comprises an oxide of zirconium.

12. The FET of claim 8, wherein the metal oxide is an oxide of rare earth element that has a higher heat of formation than silicon dioxide.

13. The FET of claim 8, further comprising a gate electrode overlying the metal oxide layer;

and source/drain terminals disposed in the substrate substantially adjacent the gate electrode.

14. A field effect transistor (FET) comprising:

a high-k metal oxide gate insulator disposed over a substantially intrinsic layer of silicon which overlies a silicon substrate;

a gate electrode overlying the metal oxide layer; and

source/drain terminals disposed in the substrate substantially adjacent the gate electrode.

15. The FET of claim 14, wherein the metal oxide comprises an oxide of hafnium.

16. The FET of claim 14, wherein the metal oxide comprises an oxide of zirconium.

17. The FET of claim 14, wherein the metal oxide is an oxide of rare earth element that has a higher heat of formation than silicon dioxide.

18. The FET of claim 14, wherein the metal oxide is a metal that does not react with silicon to form a silicide.

19. The FET of claim 14, wherein the substantially intrinsic layer of silicon is an epitaxial layer.

20. The FET of claim 19, wherein the epitaxial layer has a thickness in the range of approximately 10 angstroms to 20 angstroms.

21. An apparatus, comprising:

a single crystal silicon substrate;

a substantially intrinsic layer of silicon on the single crystal silicon substrate;

a metal oxide layer on the substantially intrinsic layer of silicon; and

a polysilicon layer on the metal oxide layer.

22. The apparatus of claim 21 wherein the substantially intrinsic layer of silicon is epitaxial.

23. The apparatus of claim 21, wherein the polysilicon layer is a heavily doped gate electrode and further comprising source/drain terminals disposed in the substrate substantially adjacent the gate electrode.

24. The apparatus of claim 21, wherein the metal oxide layer comprises an oxide of hafnium.

25. The apparatus of claim 21, wherein the metal oxide layer comprises an oxide of zirconium.

26. The apparatus of claim 21, wherein the metal oxide layer is a high-k material.