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Vacuum sealed package for semiconductor chip

  • US 6,528,875 B1
  • Filed: 04/20/2001
  • Issued: 03/04/2003
  • Est. Priority Date: 04/20/2001
  • Status: Active Grant
First Claim
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1. A vacuum sealed package comprising:

  • a substrate having a conductive interconnect pattern that extends through the substrate and includes I/O terminals on an exterior surface thereof, said substrate including at least one hole extending through said substrate;

    a chip mounted on said substrate and electrically connected to said interconnect pattern;

    a lid bonded to said substrate, wherein said substrate and said lid define a cavity enclosing said chip and said hole has a first end at an interior surface of the cavity and an opposite second end at said exterior surface of the substrate;

    a metal coating lining said hole, wherein said coating is formed at said first end and extends only part of a distance between said first end and said second end; and

    a plug fused to said coating and blocking said hole so that said cavity is held in an evacuated state.

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