Scalable two transistor memory device

• US 6,528,896 B2
• Filed: 06/21/2001
• Issued: 03/04/2003
• Est. Priority Date: 06/21/2001
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Woosik, Kang, Hokyu, Song, Seungheon
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): HO, TU TU V
• Application Number:
  US09/884,911
• Publication Number:
  US 20020196649A1
• Time in Patent Office: 621 Days
• Field of Search: 257/903, 257/904, 257/331, 365/63
• US Class Current: 257/327
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: Y10S 257/904 with passive components,, e.g. polysilicon resistors

Abstract

A Scalable Two-Transistor Memory (STTM) cell array having a 4F² unit cell area, where F is the minimum feature size. The data lines and the bit lines alternate and are adjacent to each other along the Y-axis direction, and the word lines are laid out along the X-axis direction. Each STTM cell consists of a floating gate MOS sensing transistor at the surface of a semiconductor substrate, with a vertical double sidewall gate multiple tunnel junction barrier programming MOS transistor on top of the sensing transistor. A data line connects all source regions of the programming transistors and a bit line connects all the source/drain regions of the sensing transistors in a column direction. A word line connects all double sidewall gate regions of programming transistors in a row direction. This invention also deals with a column addressing circuit as well as the driving method for the circuit.

Claims

1. A semiconductor device having a scalable two-transistor memory (STTM) cell array comprising:

a semiconductor substrate;

a plurality of memory cells on the substrate arranged in a planar matrix having an x-axis and a y-axis;

each memory cell having a bottom transistor and a top transistor in a stacked configuration;

island type isolation regions located in the substrate between and adjacent to memory cells, the island type isolation regions and the adjacent memory cells forming columns parallel to the y-axis of the matrix with source and drain regions of the bottom transistor located between the columns;

three types of control lines, including bit lines, data lines, and word lines, each bit line and data line extending in a direction parallel with the y-axis in an alternating manner and the word line extending in a direction parallel with the x-axis;

wherein each bit line being electrically connected to source/drain regions of adjacent bottom transistors along each column, each data line being electrically connected to the source regions of top transistors along each column of the island type isolation regions and adjacent memory cells, and each word line being electrically connected to gates of the top transistors in a row; and

whereby a unit cell of the plurality of memory cells occupies a minimum area equal to 4F², where F represents a minimum feature size.

2. The semiconductor scalable two-transistor memory (STTM) cell array as claimed in claim 1, wherein F is represented by a width of a data line, a bit line or a word line or a distance between two adjacent data lines, bit lines or word lines.

3. The semiconductor scalable two-transistor memory (STTM) cell array as claimed in claim 1, wherein the bottom transistor is a floating gate MOSFET and the top transistor is a vertical double sidewall gated MOSFET with a multiple tunnel junction (MTJ) barrier sandwiched between a source and a drain, and the floating gate of the bottom transistor functioning as the drain of the top transistor and the source of the top transistor is available as a node at the top of the cell.

4. A semiconductor scalable two-transistor memory cell array as claimed in claim 1, wherein the semiconductor substrate material is selected from the group consisting of silicon, silicon-germanium, silicon-germanium on silicon, silicon-germanium-carbide on silicon, and silicon on insulator (SOI).

5. A semiconductor scalable two-transistor memory cell array as claimed in claim 3, wherein the multiple tunnel junction barrier consists of alternating layers of a low band gap semiconductor layer and a large band gap insulator layer.

6. A semiconductor scalable two-transistor memory cell array as claimed in claim 5, wherein the number of alternating layers forming the multiple tunnel junction barrier is between 2 to 20 layers.

7. A semiconductor scalable two-transistor memory cell array as claimed in claim 5, wherein the alternating low band gap semiconductor layers of the multiple tunnel junction barrier have a band gap of less than 3.5 eV.

8. A semiconductor scalable two-transistor memory cell array as claimed in claim 7, wherein the alternating low band gap semiconductor layers of the multiple tunnel junction barrier are selected from the group consisting of silicon, germanium, silicon germanium, and silicon germanium carbide.

9. A semiconductor scalable two-transistor memory cell array as claimed in claim 5, wherein the alternating large band gap insulator layers of the multiple tunnel junction barrier have a band gap of less than 10 eV.

10. A semiconductor scalable two-transistor memory cell array as claimed in claim 9, wherein the alternating large band gap insulator layers of the multiple tunnel junction barrier are selected from the group consisting of silicon oxide, silicon nitride, silicon oxy-nitride, metal oxides, metal nitrides and metal silicates.

11. A semiconductor scalable two-transistor memory cell array as claimed in claim 1, wherein the bit lines are continuous, heavily doped regions running parallel with the Y-axis within the semiconductor substrate and also function as source/drain regions of the bottom transistors.

12. A semiconductor scalable two-transistor memory cell array as claimed in claim 11, wherein the bit lines are heavily doped silicon, metal, metal silicide, or polycide layers or their multi-layer combinations formed on top of the continuous doped source/drain regions of the bottom transistors within the semiconductor substrate along the columns.

13. A semiconductor scalable two-transistor memory cell array as claimed in claim 1, wherein the space between word lines on top of the bit lines is filled with an insulator material.

14. A semiconductor scalable two-transistor memory cell array as claimed in claim 1, wherein the data lines and word lines are selected from the group consisting of a heavily doped silicon, polycide, metal-silicides, metals, and their multi-layer combinations.

15. A semiconductor scalable two-transistor memory cell array as claimed in claim 3, wherein the source of the top transistor and the floating gate of the bottom transistor, which also functions as the drain of the top transistor, are doped semiconductors selected from the group consisting of silicon, germanium, silicon germanium, and silicon germanium carbide.

18. A semiconductor scalable two-transistor memory cell array as claimed in claim 1, wherein the bit lines and data lines are extended to the core region for making connections to an address system circuitry.

16. A method of manufacturing a scalable two-transistor memory (STTM) cell array, comprising the steps of:

forming an island type isolation regions in the substrate;

forming a planar array of memory cells having two transistors, each memory cell having a top transistor on a bottom transistor on a semiconductor substrate, the array having symmetry along an x-axis and a y-axis, the array having rows of memory cells running parallel with the x-axis and columns of memory cells running parallel with the y-axis;

forming data lines over each of the column of memory cells;

forming bit lines between all adjacent columns of memory cells; and

forming word lines over each of the row of memory cells;

whereby a unit cell of the plurality of memory cells occupies a minimum area equal to 4F², where F represents a minimum feature size.

17. A method of manufacturing a scalable two-transistor memory (STTM) cell array as claimed in claim 16, wherein F is represented by a width of a data line, a bit line or a word line or a distance between two adjacent data lines, bit lines or word lines.