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Scalable two transistor memory device

  • US 6,528,896 B2
  • Filed: 06/21/2001
  • Issued: 03/04/2003
  • Est. Priority Date: 06/21/2001
  • Status: Expired due to Fees
First Claim
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1. A semiconductor device having a scalable two-transistor memory (STTM) cell array comprising:

  • a semiconductor substrate;

    a plurality of memory cells on the substrate arranged in a planar matrix having an x-axis and a y-axis;

    each memory cell having a bottom transistor and a top transistor in a stacked configuration;

    island type isolation regions located in the substrate between and adjacent to memory cells, the island type isolation regions and the adjacent memory cells forming columns parallel to the y-axis of the matrix with source and drain regions of the bottom transistor located between the columns;

    three types of control lines, including bit lines, data lines, and word lines, each bit line and data line extending in a direction parallel with the y-axis in an alternating manner and the word line extending in a direction parallel with the x-axis;

    wherein each bit line being electrically connected to source/drain regions of adjacent bottom transistors along each column, each data line being electrically connected to the source regions of top transistors along each column of the island type isolation regions and adjacent memory cells, and each word line being electrically connected to gates of the top transistors in a row; and

    whereby a unit cell of the plurality of memory cells occupies a minimum area equal to 4F2, where F represents a minimum feature size.

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