System power control output circuit for programmable logic devices

• US 6,529,041 B1
• Filed: 03/23/2001
• Issued: 03/04/2003
• Est. Priority Date: 03/23/2001
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Erickson, Brian D., Ng, Mark M., Jenkins, Jesse H. IV
• Primary Examiner(s): Lee, Michael G.
• Assistant Examiner(s): PAIK, STEVE S
• Application Number:
  US09/816,799
• Time in Patent Office: 711 Days
• Field of Search: 326/38, 326/39, 326/40, 326/41, 326/83, 327/316
• US Class Current: 326/40
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/17784 for supply voltage
• CPC Class Codes: H03K 19/17788 for input/output [I/O] voltages

Abstract

A power control output circuit for a PLD that allows the PLD to selectively operate in either a low current (“normal”) output mode, or a high current power control mode. In one embodiment, the power control output circuit is incorporated into a special Input/Output Blocks (PC-IOB) of the PLD. When no power control function is needed, a high current output portion of the power control output circuit is deactivated by storing an associated data value a power control configuration memory cell of the PLD, and an output driver of the PC-IOB generates low current output signals on a device I/O terminal. To perform power control functions, a portion of the PLD'"'"'s programmable logic circuitry is configured to generate a power control data signal, and the high current output portion of the power control output circuit is enabled by storing a corresponding data value in the power control configuration memory cell. When the power control data signal is generated while in the high current power control mode, the high current output circuit turns on a high current transistor that generates a high current power control output signal at the device I/O terminal.

Claims

1. A circuit comprising:

an output driver for generating a first, relatively low current output signal on an integrated circuit (IC) device terminal in response to a data output signal; and

a power control output circuit connected in parallel with the output driver and including;

a high current transistor, connected between a high voltage source and the IC device terminal, for generating a second, relatively high current output signal on the IC device terminal; and

a switch, connected between the output driver and the high current transistor, said switch including a select terminal;

wherein, in a first operating mode, the switch maintains the high current transistor in a non-conducting state such that only the first output signal is transmitted to the IC device terminal by the output driver,

wherein in a second operating mode, the switch causes the high current transistor to generate the second output signal at the IC device terminal in response to the data output signal, and

wherein the first and second operating modes are selected by applying corresponding mode signals on the select terminal of the switch independent of a value of the data output signal.

2. The power control output circuit according to claim 1, wherein the output driver comprises a second transistor controlled by the data output signal, a first terminal connected to the high voltage source, and a second terminal connected to the IC device terminal,

wherein a channel of the second transistor is narrower than a channel of the high current transistor.

3. The power control output circuit according to claim 1, wherein the output driver comprises:

a buffer for generating a logic output signal; and

CMOS switch including a p-channel transistor connected in series with an n-channel transistor between the high voltage source and ground,

wherein a gate terminal of the n-channel transistor and a gate terminal of the p-channel transistor are connected to an output terminal of the buffer, and

wherein the IC device terminal is connected to a node located between the p-channel transistor and the n-channel transistor.

4. The power control output circuit according to claim 1,

wherein the high current transistor comprises a p-channel transistor, and

wherein the switch comprises a multiplexer having a first input terminal connected to the high voltage source, a second input terminal connected to the output driver, and an output terminal connected to a gate terminal of the high current transistor.

5. The power control output circuit according to claim 1, wherein the high current transistor comprises an n-channel transistor, and

wherein the switch comprises a multiplexer having a first input terminal connected to a low voltage source, a second input terminal connected to the output driver, and an output terminal connected to a gate terminal of the high current transistor.

6. A programmable logic device (PLD) comprising:

a configuration memory array including a plurality of configuration memory cells and a power control memory cell;

programmable logic circuitry for implementing a logic operation in accordance with configuration data stored by the configuration memory cells, and for generating a data output signal in accordance with the logic operation;

a device input/output (I/O) terminal; and

a power control input/output block including;

an output driver for generating a first, relatively low current output signal on the device I/O terminal in response to the data output signal; and

a power control output circuit connected in parallel with the output driver and including;

a high current transistor, connected between a high voltage source and the device I/O terminal, for generating a second, relatively high current output signal on the IC device terminal; and

a switch connected between the output driver and the high current transistor, wherein the switch has a control terminal connected to the power control memory cell of the configuration memory array for controlling a value applied to the control terminal independent of a value of the data output signal.

7. The PLD according to claim 6, wherein the output driver comprises a second transistor controlled by the data output signal, a first terminal connected to the high voltage source, and a second terminal connected to the device I/O terminal,

wherein a channel of the second transistor is narrower than a channel of the high current transistor.

8. The PLD according to claim 6, wherein the output driver comprises:

a buffer for receiving the data output signal from the programmable logic circuitry and for generating a logic output signal; and

CMOS switch including a p-channel transistor connected in series with an n-channel transistor between the high voltage source and ground,

wherein a gate terminal of the n-channel transistor and a gate terminal of the p-channel transistor are connected to an output terminal of the buffer, and

wherein the device I/O terminal is connected to a node located between the p-channel transistor and the n-channel transistor.

9. The PLD according to claim 6,

wherein the high current transistor comprises a p-channel transistor, and

wherein the switch comprises a multiplexer having a first input terminal connected to the high voltage source, a second input terminal connected to the output driver, an output terminal connected to a gate terminal of the high current transistor, and a select terminal connected to the power control memory cell of the configuration memory array.

10. The PLD according to claim 6,

wherein the high current transistor comprises an n-channel transistor, and

wherein the switch comprises a multiplexer having a first input terminal connected to a low voltage source, a second input terminal connected to the output driver, an output terminal connected to a gate terminal of the high current transistor, and a select terminal connected to the power control memory cell of the configuration memory array.

11. The PLD according to claim 6,

wherein the high current transistor comprises a p-channel transistor,

wherein the switch comprises a multiplexer having a second input terminal connected to the high voltage source,

wherein when the power control memory cell stores a first data value, the switch passes the output signal to the gate terminal of the high current transistor, thereby turning on the high current transistor each time the data output signal is in a first state, and

wherein when the power control memory cell stores a second data value, the switch connects the voltage source to the gate terminal of the high current transistor, thereby maintaining the high current transistor in a non-conducting state.

12. The PLD according to claim 6,

wherein the high current transistor comprises an n-channel transistor,

wherein the switch comprises a multiplexer having a second input terminal connected to a low voltage source,

wherein when the power control memory cell stores a first data value, the switch passes the output signal to the gate terminal of the high current transistor, thereby turning on the high current transistor each time the output signal is in a first state, and

wherein when the power control memory cell stores a second data value, the switch connects the low voltage source to the gate terminal of the high current transistor, thereby turning off the high current transistor.

13. An electronic system comprising:

an integrated circuit (IC) device having a power terminal; and

a programmable logic device (PLD) including;

a configuration memory array including a plurality of configuration memory cells and a power control memory cell;

programmable logic circuitry for implementing a logic operation in accordance with configuration data stored by the configuration memory cells, and for generating a data output signal in accordance with the logic operation;

a device terminal; and

a power control input/output block including;

an output driver for generating a first relatively low current output signal on the device I/O terminal in response to the data output signal; and

a power control output circuit connected in parallel with the output driver and including;

a high current transistor connected between a high voltage source and the device I/O terminal for generating a second relatively high current output signal on the device I/O terminal; and

a switch connected between the output driver and the high current transistor, wherein the switch has a control terminal connected to the power control memory cell of the configuration memory array for controlling a value applied to the control terminal independent of a value of the data output signal.

14. The electronic system according to claim 13,

wherein the IC device further includes a data terminal, and

wherein the PLD further comprises:

a second device terminal connected to the data terminal of the IC device; and

an input/output block including an output driver for generating a third relatively low current output signal on the device terminal.

15. The electronic system according to claim 13, wherein the output driver of the PLD comprises a second transistor controlled by the data output signal, a first terminal connected to the high voltage source, and a second terminal connected to the device I/O terminal, wherein a channel of the second transistor is narrower than a channel of the high current transistor.

16. The electronic system according to claim 13, wherein the output driver of the PLD comprises:

a buffer for receiving the data output signal from the programmable logic circuitry and for generating a logic output signal; and

CMOS switch including a p-channel transistor connected in series with an n-channel transistor between the high voltage in source and ground,

wherein a gate terminal of the n-channel transistor and a gate terminal of the p-channel transistor are connected to an output terminal of the buffer, and

wherein the device I/O terminal is connected to a node located between the p-channel transistor and the n-channel transistor.

17. The electronic system according claim 13,

wherein the high current transistor of the PLD comprises a p-channel transistor, and

wherein the switch of the PLD comprises a multiplexer having a first input terminal connected to the high voltage source, a second input terminal connected to the output driver, an output terminal connected to a gate terminal of the configuration memory array.

18. The electronic system according to claim 13,

wherein the high current transistor of the PLD comprises an n-channel transistor, and

wherein the switch of the PLD comprises a multiplexer having a first input terminal connected to a low voltage source, a second input terminal connected to the output driver, an output terminal connected to a gate terminal of the high current transistor, and a select terminal connected to the power control memory cell of the configuration memory array.

19. The electronic system according to claim 13,

wherein the high current transistor of the PLD comprises a p-channel transistor,

wherein the switch of the PLD comprises a multiplexer having a second input terminal connected to the high voltage source,

wherein when the power control memory cell stores a first data value, the switch passes the output signal to the gate terminal of the high current transistor, thereby turning on the high current transistor each time the data output signal is in a first state, and

wherein when the power control memory cell stores a second data value, the switch connects the voltage source to the gate terminal of the high current transistor, thereby maintaining the high current transistor in a non-conducting state.

20. The electronic system according to claim 13,

wherein the high current transistor of the PLD comprises an n-channel transistor,

wherein the switch of the PLD comprises a multiplexer having a second input terminal connected to a low voltage source,

wherein when the power control memory cell stores a first data value, the switch passes the output signal to the gate terminal of the high current transistor, thereby turning on the high current transistor each time the output signal is in a first state, and

wherein when the power control memory cell stores a second data value, the switch connects the low voltage source to the gate terminal of the high current transistor, thereby turning off the high current transistor.