TOI and power compression bias network

• US 6,529,080 B1
• Filed: 09/11/2001
• Issued: 03/04/2003
• Est. Priority Date: 09/11/2001
• Status: Expired due to Term

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: Sirenza Microdevices, Inc. (Qorvo, Inc.)
• Inventors: Gittemeier, Timothy M., Cochran, Randy L., Seymour, David J.
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Choe, Henry
• Application Number:
  US09/951,686
• Time in Patent Office: 539 Days
• Field of Search: 330/149, 330/288, 330/296
• US Class Current: 330/296
• CPC Class Codes: H03F 1/302 in bipolar transistor amplifiers H03F1/303, H03F1/305, H03F1/307 take precedence
• CPC Class Codes: H03F 1/32 Modifications of amplifiers to reduce non-linear distortion by negative feedback H03F1/34
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 3/34 DC amplifiers in which all stages are DC-coupled H03F3/45 takes precedence

Abstract

An apparatus comprising an amplifier and a circuit. The amplifier may be configured to amplify an input signal. The circuit may be configured to (i) control the amplifier, (ii) compensate for non-linear characteristics of the amplifier, (iii) increase third-order intercept (TOI) and (iv) increase the output 1 dB compression point (P1 dB).

Claims

1. An apparatus comprising:

an amplifier configured to amplify an input signal; and

a control circuit (a) comprising one or more transistors connected between a collector and a base of said amplifier and (b) configured to (i) control said amplifier, (ii) compensate for non-linear characteristics of said amplifier, (iii) increase third-order intercept (TOI), and (iv) provide temperature and process variation correction to said amplifier.

2. The apparatus according to claim 1, wherein said control circuit comprises an active bias network.

3. The apparatus according to claim 1, wherein said apparatus comprises a TOI and power compensation bias network with an integrated circuit amplifier.

4. The apparatus according to claim 1, wherein said control circuit comprises:

one or more resistors;

one or more capacitors; and

one or more inductors, wherein said resistors, said transistors, said capacitors and said inductors are coupled between a power source and said amplifier.

5. The apparatus according to claim 1, wherein said control circuit is further configured to eliminate external tuning components.

6. The apparatus according to claim 1, wherein said control circuit is further configured to reduce noise.

7. The apparatus according to claim 1, wherein said control circuit is further configured to allow for single package integration.

8. The apparatus according to claim 1, wherein said apparatus comprises a low noise amplifier.

9. The apparatus according to claim 1, wherein said apparatus comprises a high power amplifier.

10. An apparatus comprising:

means for amplifying a signal; and

means for controlling said amplifying means, wherein said controlling means (i) comprises one or more transistors connected between a collector and a base of said amplifying means and (ii) compensates for non-linear characteristics, provides temperature and process variation correction, and increases third-order intercept (TOI).

11. A method for increasing third-order intercept (TOI) and power compensation in an amplifier comprising the steps of:

(A) amplifying an input signal; and

(B) controlling step (A) with one or more transistors connected between a collector and a base of said amplifier by (i) compensating for non-linear characteristics, (ii) increasing third-order intercept (TOI), and (iii) providing temperature and process variation correction.

12. The method according to claim 11, wherein step (B) further comprises:

actively biasing said amplifier.

13. The method according to claim 11, wherein step (B) further comprises:

eliminating external tuning components.

14. The method according to claim 11, wherein step (B) further comprises:

reducing noise of said amplifier.

15. The method according to claim 11, wherein step (B) further comprises:

implementing said amplifier in a single package integration.

16. The method according to claim 11, wherein step (B) further comprises:

providing high performance high linearity amplification.

17. The method according to claim 11, wherein step (B) further comprises:

providing high performance low noise amplification.

18. The method according to claim 11, wherein step (B) further comprises:

providing high performance power amplification.

19. The method according to claim 11, wherein step (B) further comprises:

providing improved linearity.