Clock control circuit

• US 6,529,083 B2
• Filed: 03/30/2000
• Issued: 03/04/2003
• Est. Priority Date: 08/12/1999
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Fujitsu Limited
• Inventors: Fujita, Atsushi
• Primary Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US09/538,523
• Publication Number:
  US 20020047748A1
• Time in Patent Office: 1,069 Days
• Field of Search: 331/49, 331/74, 331/DIG.2, 713/503, 375/376, 327/144, 327/147, 327/150
• US Class Current: 331/49
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: Y10S 331/02 Phase locked loop having lock indicating or detecting means

Abstract

In a clock control circuit, a multiplication factor setting unit outputs a multiplication factor. A buffer circuit holds a previous multiplication factor and the multiplication factor output by the multiplication factor setting unit and compares the two multiplication factors. When the multiplication factors are different from each other, a clock state control circuit provides a control to, stop the output of clock to the outside, switch the clock to a clock other than those output by the PLL oscillation circuit, change the multiplication factor in the PLL oscillation circuit, switch the clock to clock output by the PLL oscillation circuit after the PLL output clock is stabilized, and restart output of the clock to the outside.

Claims

1. A clock control circuit comprising:

a PLL oscillator which receives a reference clock from an outside and outputs a PLL output clock based on the reference clock;

a detector which outputs a state detection signal indicating stableness or unstableness of the PLL output clock;

a clock source selector which receives the reference clock and the PLL output clock and selectively outputs either of the reference clock and the PLL output clock as a basic clock;

an output circuit which receives the basic clock, generates an operating clock to be output to the outside based on the basic clock, and controls output of the operating clock to the outside; and

a clock state controller which receives the state detection signal and controls said clock source selector and said output circuit based on the state detection signal;

wherein, when the state detection signal indicates that the PLL output clock is unstable, said clock state controller controls said output circuit so as to stop the output of the operating clock to the outside and controls said clock source selector so as to select the reference clock as the basic clock; and

when the state detection signal indicates that the PLL output clock has become stable, said clock state controller controls said clock source selector so as to switch the basic clock from the reference clock to the PLL output clock and controls said output circuit so as to restart the output of the operating clock to the outside.

2. The clock control circuit according to claim 1, wherein said output circuit further comprising:

one or a plurality of frequency dividers for generation of frequency-divided clock which divide a frequency of the basic clock and generate the operating clock.

3. A clock control circuit comprising:

a PLL oscillator which generates a PLL output clock to be output to the outside based on a reference clock and a feed-back clock;

a frequency divider for generation of the feed-back clock by dividing a frequency of the PLL output clock output by said PLL oscillator;

a multiplication factor setting unit which outputs multiplication factor setting data for setting a multiplication factor in said PLL oscillator;

a buffer unit which fetches the multiplication factor setting data from said multiplication factor setting unit when fetching of the multiplication factor setting data is allowed, and outputs the fetched multiplication factor setting data to said frequency divider for generation of the feed-back clock;

a comparator which compares the multiplication factor setting data output by said multiplication factor setting unit with the multiplication factor setting data output by said buffer unit;

a clock source selector which changes over the clock source between the PLL output clock and the reference clock and outputs a basic clock; and

a clock state controller which provides first control when a result of comparison in said comparator indicates that the two multiplication factor setting data are different from each other, said first control including stopping output of an operating clock which is generated based on the basic clock to the outside;

controlling said clock source selector so as to switch the clock source from the PLL output clock to the reference clock; and

making the multiplication setting data output by said buffer unit identical to the multiplication setting data output by said multiplication factor setting unit, and provides a second control when the PLL output clock is stabilized, said second control including controlling said clock source selector so as to switch the clock source from the reference clock back to the PLL output clock;

generating the operating clock based on the PLL output clock; and

outputting the operating clock to the outside.

4. The clock control circuit according to claim 3 further comprising:

a difference detection unit which obtains a difference between the multiplication factor setting data output by said multiplication factor setting unit and the multiplication factor setting data output by said buffer unit and outputs the difference; and

one or a plurality of frequency dividers for generation of frequency-divided clock which sets into itself a frequency division ratio based on switching of the clock source by said clock source selector and the difference between the two multiplication factor setting data output by said difference detection unit, and generates the operating clock by dividing a frequency of the basic clock according to the set frequency division ratio.

5. The clock control circuit according to claim 4, wherein said frequency divider for generation of feed-back clock outputs a first operation timing signal to at least one of said frequency dividers is for generation of frequency-divided clock, and the frequency divider for generation of frequency-divided clock having received the first operation timing signal outputs the operating clock to be output to the outside in synchronization with the PLL output clock based on the first operation timing signal and outputs a second operation timing signal based on the first operation timing signal.

6. The clock control circuit according to claim 5 further comprising:

a counter which receives the second operation timing signal and synchronizes, based on the second operation timing signal, the operation of the other frequency dividers for generation of frequency-divided clock at an offset timing which can be set as desired.

7. A clock control circuit comprising:

a PLL oscillator which generates a PLL output clock based on a reference clock;

a detector which detects stableness or unstableness in the PLL output clock;

a clock source selector which receives the reference clock and the PLL clock, selects any one of the two clocks and outputs the selected clock as a basic clock;

a clock processing unit which receives the basic clock output by said clock source selector, processes the received clock and outputs the processed clock to the outside as an operating clock; and

a clock state controller which receives a result of detection in said detector and controls the operation of at least said clock source selector and said clock processing unit,

wherein said clock state controller controls said clock processing unit so as to stop the output of the operating clock to the outside, and controls said clock source selector so as to select and output the reference clock when said clock state controller receives a result of detection from said detector that indicates that the PLL output clock is unstable, and said clock state controller controls said clock source selector so as to select and output the PLL output clock as the basic clock, controls said clock processing unit so as to generate the operating clock based on the PLL output clock output by said clock source selector and output the operating clock to the outside when said clock state controller receives a result of detection from said detector that indicates that the PLL output clock has become stable.

8. The clock control circuit according to claim 7 further comprising an oscillator which generates and outputs the reference clock.

9. The clock control circuit according to claim 7, wherein said clock processing unit has at least one frequency divider which divides the frequency of the basic clock obtained from said clock source selector and outputs the frequency-divided clock to the outside as the operating clock.

10. A clock control circuit comprising:

a PLL oscillator which generates a PLL output clock based on a reference clock and a feed-back clock using a multiplication factor;

a feed-back clock generator which receives the PLL output clock of said PLL oscillator, generates the feed-back clock by dividing a frequency of the PLL output clock and outputs the feed-back clock to said PLL oscillator;

a multiplication factor setting unit which outputs a multiplication factor setting data to be utilized for setting the multiplication factor in said PLL oscillator;

a buffer unit which stores the multiplication factor setting data output by said multiplication factor setting unit, and outputs the multiplication factor setting data to said feed-back clock generator, and overwrites the multiplication factor setting data onto an existing multiplication factor setting data when it receives a fetch signal;

a comparator which receives the multiplication factor setting data from said multiplication factor setting unit and the multiplication factor setting data from said buffer unit and compares the two multiplication factor setting data;

a clock source selector which receives the reference clock and the PLL output clock, selects any one of the two clocks and outputs the selected clock as a basic clock;

a clock processing unit which receives the basic clock output by said clock source selector, processes the received clock and outputs the processed clock to the outside as an operating clock; and

a clock state controller which receives a result of comparison in said comparator, generates and outputs the fetch signal to said buffer unit, and controls the operation of at least said clock source selector and said clock processing unit,

wherein said clock state controller controls said clock processing unit so as to stop the output of the operating clock to the outside, controls said clock source selector so as to select and output the reference clock as the basic clock, outputs the fetch signal thereby controlling said buffer unit so as to overwrite the multiplication factor setting data obtained from said multiplication factor setting unit onto the existing multiplication factor setting data, controls said clock source selector so as to select and output the PLL output clock as the basic clock, controls said clock processing unit so as to generate the operating clock based on the PLL output clock output by said clock source selector and output the operating clock to the outside when said clock state controller receives a result of comparison from said comparator that indicates that the two multiplication factor setting data are different from each other.

11. The clock control circuit according to claim 10 further comprising an oscillator which generates and outputs the reference clock.

12. The clock control circuit according to claim 10 further having a difference calculating unit which receives the multiplication factor setting data from said multiplication factor setting unit and the multiplication factor setting data from said buffer unit and calculates a difference between the two multiplication factor setting data,

said clock processing unit having,

at least one frequency divider which divides the frequency of the basic clock obtained from said clock source selector based on a frequency division ratio and outputs the frequency-divided clock to the outside as the operating clock; and

a frequency division ratio setting unit which receives an information about the basic clock output by said clock source selector and also receives the difference between the two multiplication factor setting data from said difference calculating unit, and sets the frequency division ratio in said frequency divider based on the basic clock output by said clock source selector and the difference between the two multiplication factor setting data.

13. The clock control circuit according to claim 12, wherein said feedback clock generator outputs a timing signal corresponding to its own operation timing to at least one frequency divider in said clock processing unit, and

said frequency divider that received the timing signal from said feed-back clock generator outputs the frequency-divided clock to the outside in synchronization with the basic clock obtained from said clock source selector based on the timing signal.

14. The clock control circuit according to claim 10 further having a difference calculating unit which receives the multiplication factor setting data from said multiplication factor setting unit and the multiplication factor setting data from said buffer unit and calculates a difference between the two multiplication factor setting data,

said clock processing unit having,

a plurality of frequency dividers which divide the frequency of the clock obtained from said clock source selector based on a frequency division ratio and outputs the frequency-divided clock to the outside as the operating clock, wherein at least one of the plurality frequency dividers outputs a timing signal corresponding to its own operation timing;

a frequency division ratio setting unit which receives an information about the basic clock output by said clock source selector and also receives the difference between the two multiplication factor setting data from said difference calculating unit, and sets the frequency division ratio in said frequency dividers based on the basic clock output by said clock source selector and the difference between the two multiplication factor setting data; and

synchronization unit which receives the timing signal and synchronizes the operation of the other frequency divider to the operation of said frequency divider from which the timing signal is received based on the timing signal at a pre-set offset timing.

15. The clock control circuit according to claim 14, wherein said clock processing unit further having an offset timing setting unit for setting the offset timing in said synchronization unit.

16. The clock control circuit according to claim 14, wherein said synchronization unit receives the basic clock output by said clock source selector, starts counting a time from a point of time when the timing signal is received, and synchronizes the operation of the other frequency divider to the operation of said frequency divider from which the timing signal is received when the counted time is equal to the offset timing.

17. The clock control circuit according to claim 10 further comprising a multiplication factor changing unit which changes the multiplication factor setting data in said multiplication factor setting unit.

18. A clock control method comprising:

a detection step of detecting stableness or unstableness of a PLL output clock which is output from a PLL oscillator based on a reference clock;

a first control step on stopping output of an operating clock which is generated based on a basic clock to the outside and selecting the reference clock as the basic clock when unstableness of the PLL output clock is detected;

a second control step of switching the basic clock from the reference clock to the PLL output clock and restarting the output of the operating clock to the outside when stableness of the PLL output clock has been detected.

19. A clock control method comprising:

a comparison step on comparing a multiplication factor setting data to be set newly with a current multiplication factor setting data, said multiplication factor setting data setting a multiplication factor in a PLL oscillator which generates a PLL output clock based on a reference clock;

a first control step on stopping output of an operating clock which is generated based on a basic clock and output to the outside, selecting the reference clock as the basic clock, and making the current multiplication factor setting data identical to the multiplication factor setting data to be set newly when a result of the comparison in said comparison step indicates that the two multiplication factor setting data is different from each other;

a second control step of switching the basic clock from the reference clock to the PLL output clock and restarting the output of the operating clock to the outside when the PLL output clock has been stabilized.