Video processor using shared memory space

• US 6,529,249 B2
• Filed: 03/13/1998
• Issued: 03/04/2003
• Est. Priority Date: 03/13/1998
• Status: Expired due to Term

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: Oak Technology Partners (Qualcomm, Inc.)
• Inventors: Hashemi, Mark Vahid
• Primary Examiner(s): Miller, John
• Assistant Examiner(s): Lo, Linus H.
• Application Number:
  US09/042,424
• Publication Number:
  US 20020071060A1
• Time in Patent Office: 1,817 Days
• Field of Search: H04/N.964, 348/711, 348/714, 348/715, 348/716, 348/717, 348/718, 348/719, 348/720, 345/514, 345/515, 345/518, 345/519, 345/541, 345/543, 358/147
• US Class Current: 348/714
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/42 characterised by the display of patterns using a display memory without fixed position correspondence between the display memory contents and the display position on the screen
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/427 Display on the fly, e.g. simultaneous writing to and reading from decoding memory
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/4435 Memory management allocation of memory to service a request G06F9/5016; addressing or allocating within memory systems or architectures G06F12/02
• CPC Class Codes: H04N 9/641 Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence

Abstract

Memory requirements in a video processor and display system are reduced by storing in memory processed video signals for a plurality of regions of a picture, processing video signals for additional regions of a picture while stored video signals are retrieved in controlling a display, and then storing the newly processed video signals in the memory space occupied by the retrieved video signals. An entire reconstructed frame of image signals is not needed in order to begin the display of the same frame, certain regions of the frame can be displayed while other regions are still being reconstructed. Overwrite protection is provided for stored image signals until the stored image signals are retrieved for image display.

Claims

1. A video processor and display system comprising:

a) a processor for receiving and processing video signals to provide digital display control signals for a first plurality of display frame regions, said video signals including two fields of interlaced raster scan lines,

b) a memory coupled to the processor for storing said digital display control signals, said memory having a storage capacity of one field of a frame and a portion of a second field of a frame but less than video display signals for one complete display picture frame, said memory including means to prevent erasure of stored video signals until the stored video signals are retrieved for video display control, and then allowing new video data for part of a display picture frame to write over the retrieved video signals for another part of the display picture frame, whereby new video signals for a picture frame are being stored as other video signals for the picture frame are being retrieved, said memory being divided into a second plurality of memory regions, said second plurality being different in number from said first plurality of display frame regions, said processor generating pointers to said second plurality of memory regions for video signals corresponding to one of said first plurality of display frame regions, and

c) a video display for receiving video signals from said memory for use in controlling a raster scan in the display, said display being divided into the first plurality of display frame regions, said processor processing video signals for one of said first plurality of display frame regions while video signals are retrieved from memory for another one of the first plurality of display frame regions.

2. The video processor and display system is defined by claim 1 wherein said first plurality of display frame regions includes 6 top field regions and 6 bottom field regions.

3. The video processor and display system as defined by claim 2 wherein said second plurality of memory regions comprises 9 regions, the 12 field regions of video signals cycling through said 9 regions of memory with video signals retrieved from a region of memory for picture frame control being replaced by newly processed video signals for the picture frame.