Semiconductor memory

• US 6,529,401 B2
• Filed: 07/10/2001
• Issued: 03/04/2003
• Est. Priority Date: 12/06/2000
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Nii, Koji
• Primary Examiner(s): Le, Vu A.
• Assistant Examiner(s): LE, TOAN K
• Application Number:
  US09/900,917
• Publication Number:
  US 20020067637A1
• Time in Patent Office: 602 Days
• Field of Search: 365/154, 365/159, 365/156, 365/155
• US Class Current: 365/154
• CPC Class Codes: G11C 11/4125 Cells incorporating circuit means for protecting against loss of information
• CPC Class Codes: G11C 5/005 Circuit means for protection against loss of information of semiconductor storage devices
• CPC Class Codes: H01L 27/085 including field-effect components only

Abstract

A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter includes a NMOS transistor and a PMOS transistor, and an inverter includes a NMOS transistor and a PMOS transistor. The inverters are subjected to cross section. The NMOS transistor is formed within a P well region, and NMOS transistor is formed within a P well region. The P well regions are oppositely disposed with an N well region interposed therebetween.

Claims

1. A semiconductor memory comprising:

a memory cell containing,

first and second inverters subjected to cross connection, a first conductivity type being defined by a first kind, and a second conductivity type being defined by a second kind, wherein said first inverter includes a first field effect transistor of the first kind and a first field effect transistor of the second kind, said second inverter includes a second field effect transistor of the first kind and a second field effect transistor of the second kind, and said first and second field effect transistors of the first kind are respectively disposed in separate first and second well regions of the second kind, wherein,

an output part of said first inverter includes a connecting part between one electrode of said first field effect transistor of the first kind and one electrode of said first field effect transistor of the second kind, and an input part thereof includes a connecting part between a control electrode of said first field effect transistor of the first kind and a control electrode of said first field effect transistor of the second kind,

an output part of said second inverter includes a connecting part between one electrode of said second field effect transistor of the first kind and one electrode of said second field effect transistor of the second kind, and an input part thereof includes a connecting part between a control electrode of said second field effect transistor of the first kind and a control electrode of said second field effect transistor of the second kind,

said memory cell further includes;

a third field effect transistor of the first kind, one electrode of which is connected to a first storage terminal electrically connected to said output part of said first inverter and said input part of said second inverter, and the other electrode of which is connected to a first bit line, and a control electrode of which is connected to a word line; and

a fourth field effect transistor of the first kind, one electrode of which is connected to a second storage terminal electrically connected to said output part of said second inverter and said input part of said first inverter, and the other electrode of which is connected to a second bit line, and a control electrode of which is connected to a word line, and

said third and fourth field effect transistors of the first kind are respectively disposed in said second and first well regions of the second kind.

2. The semiconductor memory according to claim 1, wherein the respective one electrodes in said first to fourth field effect transistors of the first kind are disposed separately.

3. The semiconductor memory according to claim 1, wherein

said first and third field effect transistors of the first kind and said first field effect transistor of the second kind area are arranged in an approximately straight line along the direction of formation of said first word line, and

said second and fourth field effect transistors of the first kind and said second field effect transistor of the second kind are arranged in an approximately straight line along the direction of formation of said word line.

4. The semiconductor memory according to claim 1, wherein

said first and second field effect transistors of the first kind are arranged so as to be point symmetry with respect to the central point of said memory cell.

5. The semiconductor memory according to claim 1, wherein

said third and fourth effect transistors of the first kind are arranged so as to be point symmetry with respect to the central point of said memory cell.

6. The semiconductor memory according to claim 1, wherein

the width of said control electrode of said first and second field effect transistors of the first kind is set so as to be larger than the width of said control electrode of said third and fourth field effect transistors of the first kind.

7. The semiconductor memory according to claim 1, wherein

said memory cell further includes:

a first resistance component interposed between said input part of said first inverter and said second storage terminal; and

a second resistance component interposed between said input part of said second inverter and said first storage terminal.

8. The semiconductor memory according to claim 7, wherein

said first and second resistance components include a high resistance metal wiring formed from a metal material having a higher resistivity than CoSi.

9. The semiconductor memory according to claim 7, wherein

said first and second resistance components include a high resistance polysilicon wiring formed from polysilicon having a higher resistivity than CoSi.

10. The semiconductor memory according to claim 2, wherein

said control electrodes of said third and fourth field effect transistors of the first kind and said word line are formed by using a single polysilicon.

11. The semiconductor memory according to claim 1, wherein

said word line includes separate first and second word lines,

said control electrode of said third field effect transistor of the first kind is connected to said first word line, and

said control electrode of said fourth field effect transistor of the first kind is connected to said second word line.

12. The semiconductor memory according to claim 11, wherein

said first bit line includes first and second partial bit lines forming a pair of bit lines,

said second bit line includes third and fourth partial bit lines forming a pair of bit lines,

said third field effect transistor of the first kind includes fifth and sixth field effect transistors of the first kind, said fifth field effect transistor of the first kind being interposed between said first partial bit line and said second storage terminal, said sixth field effect transistor of the first kind being interposed between said second partial bit line and said first storage terminal, and

said fourth field effect transistor of the first kind includes seventh and eighth field effect transistors of the first kind, said seventh field effect transistor of the first kind being interposed between said third partial bit line and said first storage terminal, said eighth field effect transistor of the first kind being interposed between said fourth partial bit line and said second storage terminal.

13. The semiconductor memory according to claim 12, wherein

the width of said control electrode of said first and second field effect transistors of the first kind is set so as to be larger than the width of said control electrode of said fifth to eighth field effect transistors of the first kind.

14. The semiconductor memory according to claim 1, wherein

a region for forming said control electrode of said first and second field effect transistors of the first kind is disposed so as to form a portion of said second and first storage terminals, respectively.

15. The semiconductor memory according to claim 1, wherein

said first and second field effect transistors of the second kind are disposed in a well region of the first kind, and

said well region of the first kind is disposed between said first and second well regions of the second kind.

16. The semiconductor memory according to claim 11, wherein

a region for forming said control electrode of said first and second field effect transistors of the first kind is disposed so as to form a portion of said second and first storage terminals, respectively.

17. The semiconductor memory according to claim 12, wherein

a region for forming said control electrode of said first and second field effect transistors of the first kind is disposed so as to form a portion of said second and first storage terminals, respectively.

18. The semiconductor memory according to claim 1, wherein

said first conductive type includes an N type,

said second conductive type includes a P type,

said field effect transistor of the first kind includes a NMOS transistor, and

said field effect transistor of the second kind includes a PMOS transistor.

19. The semiconductor memory according to claim 1, wherein

said first conductive type includes an N type,

said second conductive type includes a P type,

said field effect transistor of the first kind includes a NMOS transistor, and

said field effect transistor of the second kind includes a PMOS transistor.

20. A semiconductor memory comprising:

a memory cell containing,

first and second inverters subjected to cross connection, a first conductivity type being defined by a first kind, and a second conductivity type being defined by a second kind, wherein said first inverter includes a first field effect transistor of the first kind and a first field effect transistor of the second kind, said second inverter includes a second field effect transistor of the first kind and a second field effect transistor of the second kind, and said first and second field effect transistors of the first kind are respectively disposed in separate first and second well regions of the second kind,

a third field effect transistor of the first kind, one electrode of which is connected to a first storage terminal electrically connected to an output part of said first inverter and an input part of said second inverter, and the other electrode of which is connected to a first bit line, and a control electrode of which is connected to a first word line, and

a fourth field effect transistor of the first kind, one electrode of which is connected to a second storage terminal electrically connected to an output part of said second inverter and an input part of said first inverter, and the other electrode of which is connected to a second bit line, and a control electrode of which is connected to a second word line, wherein;

said third and fourth field effect transistors of the first kind are respectively disposed in said second and first well regions of the second kind,

said first and third field effect transistors of the first kind and said first field effect transistor of the second kind area are arranged in an approximately straight line along the direction of formation of said first word line, and

said second and fourth field effect transistors of the first kind and said second field effect transistor of the second kind are arranged in an approximately straight line along the direction of formation of said second word line.