Low power static memory
First Claim
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1. A low power static random access memory SRAM architecture comprising:
- the SRAM comprises a memory array which is divided into a plurality of memory subarrays;
a sense amplifier is provided for each column, having a pair of bitlines, of each memory subarray, and wherein a separate sense amplifier is provided for each column of data cells in each memory subarray, and each sense amplifier is not shared between different subarrays, such that when a set of memory cells in a memory subarray is accessed in a data read or write operation, only the memory subarray and the set of memory cells and sense circuits of interest are accessed and activated in the data read or write operation, to reduce power consumption during each data read or write operation.
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Abstract
A stacked block array architecture.for a SRAM memory for low power applications. The architecture turns on only the required data cells and sensing circuitry to access a particular set of data cells of interest. The wordline delay is reduced by using a shorter and wider wordline wire size. Although less power is consumed, the performance is improved by the reduction in loading of wordlines and bitlines.
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8 Claims
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1. A low power static random access memory SRAM architecture comprising:
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the SRAM comprises a memory array which is divided into a plurality of memory subarrays;
a sense amplifier is provided for each column, having a pair of bitlines, of each memory subarray, and wherein a separate sense amplifier is provided for each column of data cells in each memory subarray, and each sense amplifier is not shared between different subarrays, such that when a set of memory cells in a memory subarray is accessed in a data read or write operation, only the memory subarray and the set of memory cells and sense circuits of interest are accessed and activated in the data read or write operation, to reduce power consumption during each data read or write operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification