Graphics display system with unified memory architecture

• US 6,529,935 B1
• Filed: 11/14/2000
• Issued: 03/04/2003
• Est. Priority Date: 11/09/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: MacInnis, Alexander G., Tang, Chengfuh Jeffrey, Kranawetter, Greg A., Patterson, James T., Xie, Xiaodong
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US09/712,736
• Time in Patent Office: 840 Days
• Field of Search: 709/100-103, 710/240, 710/241, 710/107, 710/116, 710/40, 710/41, 710/244, 711/151, 711/100, 345/530, 345/156
• US Class Current: 718/102
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 9/00 Image coding bandwidth or redundancy reduction for static pictures H04N1/41; coding or decoding of static colour picture signals H04N1/64; methods or arrangements for coding, decoding, compressing or decompressing digital video signals H04N19/00
• CPC Class Codes: G06T 9/007 Transform coding, e.g. discrete cosine transform
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/02 : characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 5/024 : using colour registers, e.g. to control background, foreground, surface filling G09G5/06 takes precedence
• CPC Class Codes: G09G 5/026 : Control of mixing and/or overlay of colours in general G09G5/022 and G09G5/024 take precedence
• CPC Class Codes: G09G 5/06 : using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/12 : Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/14 : Display of multiple viewports
• CPC Class Codes: G09G 5/28 : for enhancement of character form, e.g. smoothing
• CPC Class Codes: G09G 5/346 : for systems having a bit-mapped display memory
• CPC Class Codes: G09G 5/36 : characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: G09G 5/363 : Graphics controllers
• CPC Class Codes: H04N 11/143 : Encoding means therefor H04N11/16 takes precedence
• CPC Class Codes: H04N 11/20 : Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards
• CPC Class Codes: H04N 19/42 : characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 : characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/436 : using parallelised computational arrangements
• CPC Class Codes: H04N 19/44 : Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/59 : involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
• CPC Class Codes: H04N 19/61 : in combination with predictive coding
• CPC Class Codes: H04N 21/42204 : User interfaces specially adapted for controlling a client device through a remote control device; Remote control devices therefor constructive details of casings for the remote control device H01H9/0235; user interfaces for controlling a tuning device of a television receiver through a remote control H03J9/00; remote control of peripheral devices connected to a television receiver through the remote control device of the television receiver H04B1/205
• CPC Class Codes: H04N 21/426 : Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/42653 : for processing graphics
• CPC Class Codes: H04N 21/4305 : Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/4316 : for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
• CPC Class Codes: H04N 21/434 : Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/440263 : by altering the spatial resolution, e.g. for displaying on a connected PDA
• CPC Class Codes: H04N 21/4438 : Window management, e.g. event handling following interaction with the user interface
• CPC Class Codes: H04N 21/47 : End-user applications
• CPC Class Codes: H04N 5/04 : Synchronising for television systems using pulse code modulation H04N7/56
• CPC Class Codes: H04N 5/126 : whereby the synchronisation signal indirectly commands a frequency generator
• CPC Class Codes: H04N 5/14 : Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 5/44504 : Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• CPC Class Codes: H04N 5/45 : Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 5/46 : for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 7/0122 : the input and the output signals having different aspect ratios
• CPC Class Codes: H04N 7/0135 : involving interpolation processes interpolation-based image scaling G06T3/4007; interpolation for video coding H04N19/587, H04N19/59
• CPC Class Codes: H04N 9/45 : Generation or recovery of colour sub-carriers
• CPC Class Codes: H04N 9/641 : Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence
• CPC Class Codes: H04N 9/642 : Multi-standard receivers

Abstract

A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.

Claims

1. A unified memory system comprising:

a memory that is shared by a plurality of devices; and

a memory request arbiter coupled to the memory, wherein the memory request arbiter performs real time scheduling of memory requests from different devices having different priorities, the unified memory system provides for real time scheduling of tasks, some of which do not inherently have pre-determined periodic behavior and provides access to memory by requesters that are sensitive to latency and do not have determinable periodic behavior.

2. The unified memory system of claim 1 wherein a predetermined interval between subsequent accesses by a task is enforced.

3. The unified memory system of claim 1 further comprising a block out timer, the block out timer being associated with one or more devices and coupled between the associated devices and the memory request arbiter, wherein the block out timer is used to enforce a predetermined interval between subsequent accesses by the associated devices.

4. The unified memory system of claim 3 wherein the devices associated with the block out timer include a CPU.

5. The unified memory system of claim 3 wherein the devices associated with the block out timer make high priority service requests through the block out timer.

6. The unified memory system of claim 5 wherein the block out timer blocks out the high priority service request made by the associated devices while the block out timer is running until the block out timer times out.

7. The unified memory system of claim 6 wherein the block out timer is started when any one of the associated devices makes the high priority service request.

8. The unified memory system of claim 6 wherein the block out timer is started when the high priority service request made by any one of the associated devices is serviced.

9. The unified memory system of claim 6 wherein the block out timer is started some time between the time any one of the associated devices makes the high priority service request and the time when the high priority service request is serviced.

10. The unified memory system of claim 3 wherein a block out period of the block out timer is programmable.

11. The unified memory system of claim 3 further comprising a round robin server for handling low priority tasks, wherein one or more devices that are associated with the block out timer are coupled to the round robin server as low priority tasks, and the round robin server requests service to the memory request arbiter for one of the low priority tasks coupled to the round robin server at a time in a round robin manner.

12. The unified memory system of claim 11 wherein the devices that are associated with the block out timer are handled as one of the low priority tasks whenever the block out timer is running.

13. The unified memory system of claim 3 wherein the block out timer is associated with one of the devices, is coupled between the associated device and the memory request arbiter, and is used to enforce the predetermined time interval between subsequent accesses by the associated device.

14. The unified memory system of claim 3 wherein the block out timer is associated with two or more devices, is coupled between the associated devices and the memory request arbiter, and is used to enforce the predetermined time interval between subsequent accesses by the associated devices.

15. The unified memory system of claim 3 wherein the predetermined interval is an interval within which a same one of the associated devices is not allowed to access memory more than once.

16. The unified memory system of claim 3 wherein at least one of the associated devices has its predetermined interval that is different from the predetermined interval of at least one other one of the associated devices.

17. The unified memory system of claim 1 further comprising dual memory controllers, the dual memory controllers including a first memory controller and a second memory controller, the memory request arbiter including a first arbiter coupled to the first memory controller and a second arbiter coupled to the second memory controller, wherein the first arbiter and the second arbiter perform real time scheduling of memory requests separately and independently of each other.

18. A method of designing real time scheduling comprising the steps of:

running a critical instant analysis;

ordering periods of different tasks from shortest to longest;

assigning priorities based on the order in accordance to the duration of the periods;

selecting tasks that are non-periodic but requires expedited servicing, assigning high priorities to them, and imposing a predetermined interval between successive accesses by these tasks; and

assigning low priority to non-periodic tasks, that do not require expedited servicing, to be serviced in a round robin manner.

19. The method of designing real time scheduling of claim 18 wherein the step of running a critical instant analysis comprises the steps of assuming all tasks request service at a critical instant, assuming a task is being serviced at the critical instant, and determining whether or not all tasks can be serviced within a period of each task.

20. The method of designing real time scheduling of claim 18 wherein the design for real time scheduling is re-evaluated if the critical instant analysis fails.

21. The method of designing real time scheduling of claim 18 wherein the predetermined interval between successive accesses by the high priority tasks that are non-periodic but requires expedited servicing is imposed by coupling a block out timer between each of these tasks and a memory request arbiter, such that high priority service request by each of these tasks is blocked out while the block out timer coupled to the task is running.

22. The method of designing real time scheduling of claim 21 wherein the block out timer is designed to start running upon making of the high priority service request by the coupled task.

23. The method of designing real time scheduling of claim 21 wherein the block out timer is designed to start running upon servicing of the high priority service request made by the coupled task.

24. The method of designing real time scheduling of claim 21 wherein the block out timer is designed to start running some time between the time the high priority service request is made by the coupled task and that high priority service request is serviced.

25. The method of designing real time scheduling of claim 21 wherein the tasks coupled to the block out timer are also coupled to a round robin server that handles service requests from these tasks as low priority requests in a round robin manner while the block out timer is running.

26. The method of designing real time scheduling of claim 18 wherein real time scheduling is implemented independently to first and second arbiters.

27. The method of designing real time scheduling of claim 26 wherein the first arbiter is coupled to a first memory controller and the second arbiter is coupled to a second memory controller, and wherein the first and second memory controllers control first and second memory spaces that are contiguous to each other.

28. The method of claim 18 wherein the predetermined interval is an interval within which a same one of the selected tasks is not allowed to access memory more than once.

29. The method of claim 18 wherein at least one of the selected tasks has its predetermined interval that is different from the predetermined interval of at least one other one of the selected tasks.