Semiconductor devices and methods of manufacturing the same

• US 6,531,356 B1
• Filed: 01/27/2000
• Issued: 03/11/2003
• Est. Priority Date: 01/27/1999
• Status: Active Grant

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Hayashi, Masahiro
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): LEE, HSIEN MING
• Application Number:
  US09/491,923
• Time in Patent Office: 1,139 Days
• Field of Search: 438/294, 438/297, 438/298, 438/301, 438/306, 438/288, 438/225, 438/224, 438/227, 438/228, 257/327, 257/336-339, 257/404
• US Class Current: 438/228
• CPC Class Codes: H01L 21/76202 using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO H01L21/76235 takes precedence; together with vertical isolation, e.g. LOCOS in a SOI substrate, H01L21/76264
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]

Abstract

Embodiments include a semiconductor device including a well structure such that well areas can be formed with a higher density of integration and a plurality of high-voltage endurable transistors can be driven independently of one another with different voltages, and a method of manufacturing the semiconductor device. The semiconductor device may include a triple well comprising a first well formed in a silicon substrate and having a first conductivity type (P-type), a second well formed in adjacent relation to the first well and having a second conductivity type (N-type), and a third well formed in the second well and having the first conductivity type (P-type). A high-voltage endurable MOSFET is provided in each of the wells. Each MOSFET has an offset area in the corresponding well around a gate insulating layer. The offset area is formed of a low-density impurity layer which is provided under an offset LOCOS layer on the silicon substrate.

Claims

1. A method of manufacturing a semiconductor device, comprising:

selectively forming, on a semiconductor substrate, an oxidation-resistant layer having a masking action against oxidation;

introducing an impurity of second conductivity type to said semiconductor substrate with said oxidation-resistant layer used as a mask, thereby forming a second well in said semiconductor substrate;

selectively oxidizing a surface area of said second well with said oxidation-resistant layer used as a mask, thereby forming a LOCOS layer in said second well;

removing said oxidation-resistant layer;

introducing an impurity of first conductivity type to said semiconductor substrate with said LOCOS layer used as a mask, thereby forming a first well in said semiconductor substrate in adjacent relation to said second well;

removing said LOCOS layer;

introducing an impurity of the first conductivity type to part of said second well, thereby forming a third well in said second well; and

forming a field effect transistor in each of said first, second and third wells, by a process comprising;

after introducing a first conductivity type impurity and a second conductivity type impurity in areas of said semiconductor substrate, forming a LOCOS layer in a pattern on said semiconductor substrate to form first conductivity type and second conductivity type low-density impurity layers in said areas under the LOCOS layer, part of said LOCOS layer being formed at least around a gate insulating layer of said field effect transistor;

forming a gate electrode; and

forming a high-density impurity layer comprising a source/drain area.

2. A method of manufacturing a semiconductor device according to claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type.

3. A method of manufacturing a semiconductor device according to claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type.

4. A method of manufacturing a semiconductor device according to claim 1, wherein the depth of said third well is about ½

to about ⅓

of the depth of said second well.

5. A method of manufacturing a semiconductor device according to claim 1, wherein said second well has a depth of 15-18 μ

m and said third well has a depth of 6-8 μ

m.

6. A method of manufacturing a semiconductor device according to claim 1, wherein said first well has an impurity density of 1×

10¹⁶-3×

10¹⁶ atoms/cm³, said second well has an impurity density of 1×

10¹⁶-3×

10¹⁶ atoms/cm³, and said third well has an impurity density of 1×

10¹⁶-3×

10¹⁶ atoms/cm³.

7. A method of manufacturing a semiconductor device according to claim 1, wherein, around the high-density impurity layer comprising the source area or the drain area of said field effect transistor, a low-density impurity layer having the same conductivity type as said high-density impurity layer is provided.

8. A method of manufacturing a semiconductor device according to claim 1, wherein said low-density impurity layer and a channel stopper layer provided under the LOCOS layer on said semiconductor substrate are contiguously provided.

9. A method of manufacturing a semiconductor device according to claim 7, wherein said low-density impurity layer and a channel stopper layer provided under the LOCOS layer on said semiconductor substrate are contiguously provided.

10. A method of manufacturing a semiconductor device according to claim 1, wherein the gate insulating layer of said field effect transistor has a film thickness of from about 60 nm to about 80 nm.

11. A method of manufacturing a semiconductor device according to claim 1, wherein said gate insulating layer of said field effect transistor has a film thickness of from 60 nm to 80 nm.

12. A method of manufacturing a semiconductor device, comprising:

forming a first well of a first conductivity type in a semiconductor substrate;

forming a second well of a second conductivity type in said semiconductor substrate;

forming a third well within said second well, said third well having said first conductivity type, said third well formed to be about ⅓

to about ½

the depth of said second well; and

forming a field effect transistor in each of said first, second and third wells, each of said transistors formed by introducing a low density impurity selected from the group consisting of an N-type impurity and a P-type impurity into areas of said semiconductor substrate, forming a LOCOS layer in a pattern on said semiconductor substrate, forming a gate electrode, and forming a high density impurity layer comprising a source/drain area, wherein at least a portion of said LOCOS layer is positioned adjacent to and in contact with a gate insulating layer and said gate electrode.

13. A method of claim 12, wherein said third well formed to be from ⅓

to ½

of the depth of said second well.

14. A method of manufacturing a semiconductor device, comprising:

forming a first well of a first conductivity type in a semiconductor substrate;

forming a second well of a second conductivity type in said semiconductor substrate;

forming a third well within said second well, said third well having said first conductivity type; and

forming a field effect transistor in each of said first, second and third wells, each of said transistors formed by introducing a low density impurity selected from the group consisting of an N-type impurity and a P-type impurity into areas of said semiconductor substrate, forming a LOCOS layer in a pattern on said semiconductor substrate, forming a gate electrode, and forming a high density impurity layer to act as a source/drain area.

15. A method as in claim 14, wherein said third well is formed to be from ⅓

to ½

of the depth of said second well.

16. A method as in claim 14, wherein at least a portion of said LOCOS layer is positioned adjacent to and in contact with a gate insulating layer and said gate electrode.

17. A method of manufacturing a semiconductor device according to claim 14, wherein said second well has a depth of from 15 μ

m to 18 μ

m and said third well has a depth of from 6 μ

m to 8 μ

m.

18. A method of manufacturing a semiconductor device according to claim 14, wherein said first well has an impurity density of from 1×

10¹⁶ atoms/cm³ to 3×

10¹⁶ atoms/cm³, said second well has an impurity density of from 1×

10¹⁶ atoms/cm³ to 3×

10¹⁶ atoms/cm³, and said third well has an impurity density of from 1×

10¹⁶ atoms/cm³ to 3×

10¹⁶ atoms/cm³.

19. A method of manufacturing a semiconductor device according to claim 14, wherein, around said high-density impurity layer of said field effect transistor, a low-density impurity layer having the same conductivity type as said high-density impurity layer is provided.