Method for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane and ozone gases for semiconductor applications

• US 6,531,412 B2
• Filed: 08/10/2001
• Issued: 03/11/2003
• Est. Priority Date: 08/10/2001
• Status: Active Grant

• Current Assignee: International Business Machines Corporation, Samsung Electronics Co. Ltd.
• Original Assignee: Infineon Technologies AG, International Business Machines Corporation
• Inventors: Conti, Richard A., Edelstein, Daniel C., Lee, Gill Yong
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Berry, Renee R.
• Application Number:
  US09/928,209
• Publication Number:
  US 20030032306A1
• Time in Patent Office: 578 Days
• Field of Search: 438/695, 438/697, 438/712, 438/723, 438/761, 438/781, 257/750, 257/752, 257/758, 257/759, 427/255.28, 427/255.39, 427/255.393, 427/569, 427/578, 427/579
• US Class Current: 438/778
• CPC Class Codes: C23C 16/401 containing silicon
• CPC Class Codes: H01L 21/02112 characterised by the material of the layer
• CPC Class Codes: H01L 21/02129 the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
• CPC Class Codes: H01L 21/02205 the layer being characterised by the precursor material for deposition
• CPC Class Codes: H01L 21/02216 the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/3122 layers comprising polysiloxane compounds
• CPC Class Codes: H01L 21/31604 Deposition from a gas or vapour H01L21/31691, H01L21/31695 take precedence
• CPC Class Codes: H01L 21/31625 Deposition of boron or phosphorus doped silicon oxide, e.g. BSG, PSG, BPSG
• CPC Class Codes: H01L 21/31629 Deposition of halogen doped silicon oxide, e.g. fluorine doped silicon oxide
• CPC Class Codes: H01L 21/31633 Deposition of carbon doped silicon oxide, e.g. SiOC
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method is described for forming a low-k dielectric film, in particular, a pre-metal dielectric (PMD) on a semiconductor wafer which has good gap-filling characteristics. The method uses a thermal sub-atmospheric CVD process that includes a carbon-containing organometallic precusor such as TMCTS or OMCTS, an ozone-containing gas, and a source of dopants for gettering alkali elements and for lowering the reflow temperature of the dielectric while attaining the desired low-k and gap-filling properties of the dielectric film. Phosphorous is a preferred dopant for gettering alkali elements such as sodium. Additional dopants for lowering the reflow temperature include, but are not limited to boron, germanium, arsenic, fluorine or combinations thereof.

Claims

1. A pre-metal dielectric (PMD) semiconductor structure comprising:

a semiconductor wafer having features on a surface of said wafer, wherein said features are spaced to form at least one gap between said features, wherein said at least one gap has an aspect ratio greater than about 3; and

a low-k film covering said surface, wherein said low-k film fills said at least one gap without having a void, and said low-k film includes a dopant.

2. The PMD structure of claim 1 wherein said low-k film has a dielectric constant less than about 3.

3. The PMD structure of claim 1 wherein said dopant comprises phosphorous.

4. The PMD structure of claim 3 wherein said dopant further comprises a second dopant selected from the group consisting of boron, germanium, arsenic, fluorine and a combination thereof.

5. The PMD structure of claim 1 wherein said features comprise gate conductor stacks.

6. The PMD structure of claim 1 wherein said low-k film has a reflow temperature less than about 725°

C.

7. A pre-metal dielectric (PMD) semiconductor structure comprising:

a semiconductor wafer having gate conductor stacks on a surface of said wafer, said gate conductor stacks spaced to form at least one gap having an aspect ratio greater than about 3; and

a low-k film covering said surface, said low-k film having a dielectric constant less than about 3, wherein said low-k film fills said at least one gap without having a void and wherein said low-k film includes phosphorous sand a dopant selected from the group consisting of boron, germanium, arsenic, fluorine and a combination thereof.

9. The PMD structure of claim 7 wherein said low-k film has a reflow temperature of less than about 725°

C.

8. A low-k film comprising:

a carbon-containing dielectric material;

phosphorous; and

a dopant selected from the group consisting of boron, germanium, arsenic, fluorine and a combination thereof, wherein said low-k film has a dielectric constant less than about 3 and having a reflow temperature less than about 725°

C.