Electro-optical device and manufacturing method thereof

• US 6,531,713 B1
• Filed: 03/17/2000
• Issued: 03/11/2003
• Est. Priority Date: 03/19/1999
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Tran, Minh Loan
• Assistant Examiner(s): DICKEY, THOMAS L
• Application Number:
  US09/528,113
• Time in Patent Office: 1,089 Days
• Field of Search: 257/347, 257/350, 257/351, 257/357, 257/59, 257/71-72, 349/38, 349/39, 349/122, 349/138
• US Class Current: 257/59
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: H01L 2029/7863 with an LDD consisting of more than one lightly doped zone or having a non-homogeneous dopant distribution, e.g. graded LDD
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78624 the source and the drain regions being asymmetrical
• CPC Class Codes: H01L 29/78627 with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

An electro-optical device having high operation performance and reliability, and a manufacturing method thereof. A TFT structure which is strong agains hot carrier injection is realized by disposing a Lov region 207 in an n-channel TFT 203 which forms a driver circuit. Further, Loff regions 217 to 220 and offset region are disposed in an n-channel TFT 304 which forms a pixel section, and a TFT structure of low OFF current value is realized. Further, by reducing the n-type impurity element contained in Loff regions 217 to 220 to approximately 1×10¹⁶ to 5×10¹⁸ atoms/cm³, further reduction of OFF current can be performed.

Claims

1. An electro-optical device comprising a pixel section and a driver circuit over a same substrate,

wherein the driver circuit comprises a first n-channel TFT in which all of a LDD region is formed to overlap a gate wiring by interposing a gate insulating film and a second n-channel TFT in which a part of a LDD region is formed to overlap a gate wiring by interposing a gate insulating film;

a LDD region of a pixel TFT which comprises the pixel section is formed so as not to overlap a gate wiring of the pixel TFT by interposing a gate insulating film;

an offset region is formed between a channel forming region and a LDD region of the pixel TFT; and

a LDD region formed in the first n-channel TFT is formed between a drain region and a channel forming region of the first n-channel TFT, and LDD regions formed in the second n-channel TFT are formed to sandwich a channel forming region of the second n-channel TFT.

5. An electro-optical device according to claim 1 or 2 wherein at least one of the LDD region of the first n-channel TFT and the LDD region of the second n-channel TFT includes an n-type impurity element at a higher concentration than the LDD region of the pixel TFT.

6. An electro-optical device according to claim 1 or 2 wherein at least one of the LDD region of the first n-channel TFT and the LDD region of the second n-channel TFT includes an n-type impurity element at a concentration of 2 to 10 times that of the LDD region of the pixel TFT.

7. An electro-optical device according to claim 1 or 2 wherein at least one of the LDD region of the first n-channel TFT and the LDD region of the second n-channel TFT includes an n-type impurity element in a concentration range of 2×

10¹⁶ to 5×

10¹⁹ atoms/cm³ and the LDD region of the pixel TFT includes an n-type impurity element in a concentration range of 1×

10¹⁶ to 5×

10¹⁸ atoms/cm³.

8. An electro-optical device according to claim 1 or 2 wherein the offset region comprises a semiconductor film of the same composition as the channel forming region that is formed in contact with the offset region.

9. An electro-optical device according to claim 1 or 2 wherein a p-type impurity element is included in the offset region in a concentration range of 1×

10¹⁵ to 1×

10¹⁸ atoms/cm³.

10. An electro-optical device according to claim 1 or 2 wherein the pixel section comprises an EL element.

11. A electric appliance having an electro-optical device according to claim 1 or 2 used as a display section.

2. An electro-optical device comprising a pixel section and a driver circuit over a same substrate,

wherein the driver circuit comprises a first n-channel TFT in which all of a LDD region is formed to overlap a gate wiring by interposing a gate insulating film and a second n-channel TFT in which a part of a LDD region is formed to overlap a gate wiring by interposing a gate insulating film;

wherein a LDD region of a pixel TFT which comprises the pixel section is formed so as not to overlap a gate wiring of the pixel TFT by interposing a gate insulating film;

wherein a storage capacitor of the pixel section comprises a shielding film disposed on an organic resin film, an oxide of the shielding film and a pixel electrode;

wherein an offset region is formed between a channel forming region and a LDD region of the pixel TFT, and

wherein a LDD region formed in the first n-channel TFT is formed between a drain region and a channel forming region of the first n-channel TFT, and LDD regions formed in the second n-channel TFT are formed to sandwich a channel forming region of the second n-channel TFT.

3. An electro-optical device according to claim 2 wherein the shielding film is an aluminum film or a film whose principle component is aluminum.

4. An electro-optical device according to claim 2 wherein the oxide is an aluminum oxide film.

12. An electric device comprising:

at least one first thin film transistor formed over a substrate and electrically connected to a pixel electrode, said first thin film transistor comprising;

a semiconductor layer having a pair of impurity regions and a channel region extending therebetween;

a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, and

a pair of LDD regions between the channel region and the pair of impurity regions,

a driver circuit formed over the substrate for driving said at least one first thin film transistor, said driver circuit including at least a second n-channel TFT and a third n-channel TFT,

wherein said second n-channel TFT comprises;

a semiconductor layer having source and drain regions and a channel region therebetween, and an LDD region interposed between the channel region and the drain region while the source region is contiguous to the channel region; and

a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode overlaps an entire portion of the LDD region, and

wherein said third n-channel TFT comprises;

a semiconductor layer having a pair of impurity regions and a channel region therebetween, and a pair of LDD regions interposed between the channel region and the pair of impurity regions; and

a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode partly overlaps the pair of LDD regions.

20. The electric device according to claim 12 or 13 wherein said first thin film transistor comprises an offset region.

23. The electric device according to any one of claim 12, 13, 14 or 15 wherein said device is selected from the group consisting of portable telephone, video camera, mobile computer, projector personal, computer, game machine, and digital camera.

13. An electric device comprising:

at least one first thin film transistor formed over a substrate and electrically connected to a pixel electrode, said first thin film transistor comprising;

a semiconductor layer having a pair of impurity regions and a channel region extending therebetween;

a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, and

a pair of LDD regions between the channel region and the pair of impurity regions,

an interlayer insulating film comprising an organic resin formed over the first thin film transistor;

a storage capacitor electrically connected to the pixel electrode, said storage capacitor comprising;

a shielding film formed over the interlayer insulating film;

a portion of the pixel electrode overlapping the shielding film with a dielectric film interposed therebetween wherein the dielectric film comprises an oxide of a material of the shielding film,

a driver circuit formed over the substrate for driving said at least one first thin film transistor, said driver circuit including at least a second n-channel TFT and a third n-channel TFT,

wherein said second n-channel TFT comprises;

a semiconductor layer having source and drain regions and a channel region therebetween, and an LDD region interposed between the channel region and the drain region while the source region is contiguous to the channel region; and

a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode overlaps an entire portion of the LDD region, and

wherein said third n-channel TFT comprises;

a semiconductor layer having a pair of impurity regions and a channel region therebetween, and a pair of LDD regions interposed between the channel region and the pair of impurity regions; and

a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode partly overlaps the pair of LDD regions.

14. An electric device comprising:

at least one first thin film transistor formed over a substrate and electrically connected to a pixel electrode, said first thin film transistor comprising;

a semiconductor layer having a pair of impurity regions and a channel region extending therebetween;

a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, and

a pair of LDD regions between the channel region and the pair of impurity regions,

a driver circuit formed over the substrate for driving said at least one first thin film transistor, said driver circuit including at least a second n-channel TFT and a third n-channel TFT,

wherein said second n-channel TFT comprises;

a semiconductor layer having source and drain regions and a channel region therebetween, and an LDD region interposed between the channel region and the drain region while the source region is contiguous to the channel region; and

a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode overlaps an entire portion of the LDD region, and

wherein said third n-channel TFT comprises;

a semiconductor layer having a pair of impurity regions and a channel region therebetween, and a pair of LDD regions interposed between the channel region and the pair of impurity regions; and

a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode partly overlaps the pair of LDD regions,

wherein said third n-channel TFT is a part of a sampling circuit of the driver circuit.

21. The electric device according to claim 14 or 15 wherein said first thin film transistor comprises an offset region.

15. An electric device comprising:

at least one first thin film transistor formed over a substrate and electrically connected to a pixel electrode, said first thin film transistor comprising;

a semiconductor layer having a pair of impurity regions and a channel region extending therebetween;

a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, and

a pair of LDD regions between the channel region and the pair of impurity regions,

a driver circuit formed over the substrate for driving said at least one first thin film transistor, said driver circuit including at least a second n-channel TFT and a third n-channel TFT,

wherein said second n-channel TFT comprises;

a semiconductor layer having source and drain regions and a channel region therebetween, and an LDD region interposed between the channel region and the drain region while the source region is contiguous to the channel region; and

a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode overlaps an entire portion of the LDD region, and

wherein said third n-channel TFT comprises;

a semiconductor layer having a pair of impurity regions and a channel region therebetween, and a pair of LDD regions interposed between the channel region and the pair of impurity regions; and

a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode partly overlaps the pair of LDD regions,

wherein said second n-channel TFT is a part of at least one of a shift register, a frequency dividing circuit, a signal splitting circuit, a level shifter or a buffer circuit of the driver circuit.

16. An organic electroluminescence display device comprising:

at least one first thin film transistor provided at each pixel, said first thin film transistor comprising;

a semiconductor layer formed over a substrate and having a pair of impurity regions and a channel region extending therebetween;

a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, and

a pair of LDD regions between the channel region and the pair of impurity regions,

an organic electroluminescence layer provided over the substrate;

a driver circuit formed over the substrate for driving said at least one first thin film transistor, said driver circuit including at least a second n-channel TFT and a third n-channel TFT,

wherein said second n-channel TFT comprises;

a semiconductor layer having source and drain regions and a channel region therebetween, and an LDD region interposed between the channel region and the drain region while the source region is contiguous to the channel region; and

a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode overlaps an entire portion of the LDD region, and

wherein said third n-channel TFT comprises;

a semiconductor layer having a pair of impurity regions and a channel region therebetween, and a pair of LDD regions interposed between the channel region and the pair of impurity regions; and

a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode partly overlaps the pair of LDD regions.

22. The electroluminescence display device according to claim any one of claims 16, 17, 18 or 19 wherein said first thin film transistor comprises an offset region.

24. A portable telephone having an electroluminescence display device according to claim 16, 17, 18 or 19.

25. A video camera having an electroluminescence display device according to claim 16, 17, 18 or 19.

26. A mobile computer having an electroluminescence display device according to claim 16, 17, 18 or 19.

27. A personal computer having an electroluminescence display device according to claim 16, 17, 18 or 19.

28. A game machine having an electroluminescence display device according to claim 16, 17, 18 or 19.

29. A digital camera having an electroluminescence display device according to claim 16, 17, 18 or 19.

17. An organic electroluminescence display device comprising:

at least one first thin film transistor provided at each pixel, said first thin film transistor comprising;

a semiconductor layer formed over a substrate and having a pair of impurity regions and a channel region extending therebetween;

a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, and

a pair of LDD regions between the channel region and the pair of impurity regions,

an interlayer insulating film comprising an organic resin formed over the first thin film transistor;

an organic electroluminescence layer formed over the substrate;

a storage capacitor electrically connected to the pixel electrode, said storage capacitor comprising;

a shielding film formed over the interlayer insulating film;

a portion of the pixel electrode overlapping the shielding film with a dielectric film interposed therebetween wherein the dielectric film comprises an oxide of a material of the shielding film,

a driver circuit formed over the substrate for driving said at least one first thin film transistor, said driver circuit including at least a second n-channel TFT and a third n-channel TFT,

wherein said second n-channel TFT comprises;

a semiconductor layer having source and drain regions and a channel region therebetween, and an LDD region interposed between the channel region and the drain region while the source region is contiguous to the channel region; and

a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode overlaps an entire portion of the LDD region, and

wherein said third n-channel TFT comprises;

a semiconductor layer having a pair of impurity regions and a channel region therebetween, and a pair of LDD regions interposed between the channel region and the pair of impurity regions; and

a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode partly overlaps the pair of LDD regions.

18. An organic electroluminescence display device comprising:

at least one first thin film transistor provided at each pixel, said first thin film transistor comprising;

a semiconductor layer formed over a substrate and having a pair of impurity regions and a channel region extending therebetween;

a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, and

a pair of LDD regions between the channel region and the pair of impurity regions,

an organic electroluminescence layer formed over the substrate;

a driver circuit formed over the substrate for driving said at least one first thin film transistor, said driver circuit including at least a second n-channel TFT and a third n-channel TFT,

wherein said second n-channel TFT comprises;

a semiconductor layer having source and drain regions and a channel region therebetween, and an LDD region interposed between the channel region and the drain region while the source region is contiguous to the channel region; and

a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode overlaps an entire portion of the LDD region, and

wherein said third n-channel TFT comprises;

a semiconductor layer having a pair of impurity regions and a channel region therebetween, and a pair of LDD regions interposed between the channel region and the pair of impurity regions; and

a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode partly overlaps the pair of LDD regions,

wherein said third n-channel TFT is a part of a sampling circuit of the driver circuit.

19. An electroluminescence display device comprising:

at least one first thin film transistor provided at each pixel, said first thin film transistor comprising;

a semiconductor layer formed over a substrate and having a pair of impurity regions and a channel region extending therebetween;

a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, and

a pair of LDD regions between the channel region and the pair of impurity regions,

an organic electroluminescence layer formed over the substrate;

a driver circuit formed over the substrate for driving said at least one first thin film transistor, said driver circuit including at least a second n-channel TFT and a third n-channel TFT,

wherein said second n-channel TFT comprises;

a semiconductor layer having source and drain regions and a channel region therebetween, and an LDD region interposed between the channel region and the drain region while the source region is contiguous to the channel region; and

a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode overlaps an entire portion of the LDD region, and

wherein said third n-channel TFT comprises;

a semiconductor layer having a pair of impurity regions and a channel region therebetween, and a pair of LDD regions interposed between the channel region and the pair of impurity regions; and

a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode partly overlaps the pair of LDD regions,

wherein said second n-channel TFT is a part of at least one of a shift register, a frequency dividing circuit, a signal splitting circuit, a level shifter or a buffer circuit of the driver circuit.