Semiconductor integrated circuit

• US 6,531,735 B1
• Filed: 09/13/2000
• Issued: 03/11/2003
• Est. Priority Date: 09/17/1999
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Katayama, Kozo, Minami, Shinichi, Kato, Masataka, Kamigaki, Yoshiaki
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): QUINTO, KEVIN V
• Application Number:
  US09/660,923
• Time in Patent Office: 909 Days
• Field of Search: 257/314, 257/315, 257/316, 257/319, 257/320, 257/318, 257/317, 257/324
• US Class Current: 257/324
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.

Claims

1. A semiconductor integrated circuit having nonvolatile memory cells each of which comprises one memory transistor, two switch transistors and two diffusion-layer lines, wherein said memory transistor includes a gate insulating film having discrete traps and a memory gate electrode connected to a word line, said two diffusion-layer lines constitute a source line and a bit line, and the switch gate electrodes of said two switch transistors are extended along said source line and said bit line;

and

wherein said switch gate electrodes of said switch transistors which share said diffusion-layer lines are commonly connected.

2. A semiconductor integrated circuit having nonvolatile memory cells each of which comprises two memory transistors, one switch transistor and two diffusion-layer lines, wherein each of said memory transistors includes a gate insulating film having discrete traps and a memory gate electrode connected to a word line, said two diffusion-layer lines constitute a source line and a bit line, and the switch gate electrode of said one switch transistor is extended along said source line and said bit line.

3. A semiconductor integrated circuit according to claim 2, wherein each of said memory gate electrodes of said memory transistors has a width smaller than a technology feature size.

4. A semiconductor integrated circuit according to claim 2, wherein said gate insulating film having the discrete traps includes a silicon nitride film.