Integrated impedance matching and stability network

• US 6,531,740 B2
• Filed: 07/17/2001
• Issued: 03/11/2003
• Est. Priority Date: 07/17/2001
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Franson, Steven James, Bosco, Bruce Allen, Emrick, Rudy M.
• Primary Examiner(s): Tran, Minh Loan
• Assistant Examiner(s): Tran, Tan
• Application Number:
  US09/905,903
• Publication Number:
  US 20030015730A1
• Time in Patent Office: 602 Days
• Field of Search: 257/64, 257/67, 257/69, 257/71, 257/43, 257/76, 257/347, 257/195, 257/350, 257/352, 257/528, 257/531, 257/532, 257/192, 257/194, 257/190
• US Class Current: 257/347
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

An integrated circuit for intermediate impedance matching and stabilization of high power devices is disclosed. High quality epitaxial layers of monocrystalline materials grown over monocrystalline substrates enables the formation of impedance matching and stability circuits to be placed on the same substrate as the active device. Additionally, by using the manifolds of the active to form plates of a capacitor, an impedance matching network of series inductance and shunt capacitor can be compactly fabricated for increasing the output impedance to intermediate levels. The manifolds of the active device are also used to form capacitors to provide stability to high power active devices.

Claims

1. An impedance matching circuit integrated with an active device, comprising:

a monocrystalline silicon substrate;

an amorphous oxide material overlying a portion of the monocrystalline silicon substrate;

a monocrystalline perovskite oxide material overlying the amorphous oxide material; and

a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material;

said active device formed within said monocrystalline compound semiconductor material; and

said impedance matching circuit coupled to said active device and at least in part formed within said silicon substrate.

2. The impedance matching circuit of claim 1 wherein said impedance matching circuit comprising:

a capacitor having two plates, said first plate coupled to an output of said active device, said second plate coupled to ground potential;

a first inductor coupled to said first plate of said capacitor and coupled to said active device; and

a second inductor coupled to said first plate of said capacitor and forming an output for said active device.

3. The impedance matching circuit of claim 2 wherein said second plate is coupled to ground potential by way of vias in said monocrystalline silicon substrate.

4. The impedance matching circuit of claim 2 wherein said second plate is coupled to ground potential by way of a highly conductive silicon region within said monocrystalline silicon substrate.

5. The impedance matching circuit of claim 1 wherein said active device is a high frequency transistor.

6. The impedance matching circuit of claim 1 wherein said active device is a Pseudomorphic High Electron Mobility Transistor (PHEMT).

7. The impedance matching circuit of claim 1 wherein said active device is a Metal-Semiconductor-Field-Effect Transistor (MESFET).

8. An impedance matching circuit and a stability circuit integrated with an active device, comprising:

a monocrystalline silicon substrate;

an amorphous oxide material overlying the monocrystalline silicon substrate;

a monocrystalline perovskite oxide material overlying the amorphous oxide material; and

a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material;

said active device formed within said monocrystalline compound semiconductor material;

said impedance matching circuit coupled to said active device and at least in part formed within said silicon substrate; and

said stability circuit coupled to said impedance matching circuit.

9. The impedance matching circuit and stability circuit of claim 8, said impedance matching circuit comprising:

a first capacitor having two plates, said first plate coupled to an output of said active device, said second plate coupled to ground potential;

a first inductor coupled to said first plate of said first capacitor and coupled to said active device; and

a second inductor coupled to said first plate of said first capacitor and forming an output for said active device; and

said stability circuit comprising;

a second capacitor having two plates, said second capacitor formed by having a first plate integrated with an input of said active device; and

a resistor in parallel configuration to said second capacitor.

10. The impedance matching circuit and stability circuit of claim 8 wherein said active device is a high frequency transistor.

11. The impedance matching circuit and stability circuit of claim 10 wherein said second plate of said first capacitor is coupled to ground potential through vias in said substrate.

12. The impedance matching circuit and stability circuit of claim 10 wherein said resistor is fabricated on said silicon substrate.

13. The impedance matching circuit and stability circuit of claim 10 further comprising:

a second resistor in parallel configuration with said resistor.

14. The impedance matching circuit and stability circuit of claim 10 wherein said resistor is fabricated by selectively depositing resistive material between said plates of said second capacitor.

15. The impedance matching circuit and stability circuit of claim 10 wherein said second plate is coupled to ground potential by way of vias in said monocrystalline silicon substrate.

16. The impedance matching circuit and stability circuit of claim 10 wherein said second plate is coupled to ground potential by way of a highly conductive silicon region within said monocrystalline silicon substrate.

17. The impedance matching circuit and stability circuit of claim 8 wherein said active device is a Pseudomorphic High Electron Mobility Transistor (PHEMT).

18. The impedance matching circuit and stability circuit of 8 wherein said active device is a Metal-Semiconductor-Field-Effect Transistor (MESFET).