Data processing system with improved latency and associated methods

• US 6,531,889 B1
• Filed: 06/01/2001
• Issued: 03/11/2003
• Est. Priority Date: 10/10/2000
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Leitch, James R.
• Primary Examiner(s): Toker, Michael
• Assistant Examiner(s): CHO, JAMES HYONCHOL
• Application Number:
  US09/871,919
• Time in Patent Office: 648 Days
• Field of Search: 326/37-39, 326/41, 326/101
• US Class Current: 326/39
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

An configurable integrated-circuit device includes a plurality of regions that each contain electronic circuitry. The configurable integrated-circuit device also includes common circuitry adapted to provide at least one signal to at least two regions of the plurality of regions. The common circuitry and the at least two regions are positioned within the configurable integrated-circuit device so as to improve the latencies of the at least one signal to each of the at least two regions.

Claims

1. A configurable integrated-circuit device, comprising:

a plurality of regions that each include configurable electronic circuitry; and

common circuitry that provides at least one signal to at least two regions of the plurality of regions,

wherein the common circuitry comprises at least one processor circuitry, and

the common circuitry and the at least two regions are positioned within the configurable integrated-circuit device so as to improve the latencies of the at least one signal to each of the at least two regions.

2. A. The configurable integrated-circuit device of claim 1, in which the common circuitry further comprises at least one memory circuitry that communicates with the at least one processor circuitry.

3. The configurable integrated-circuit device of claim 2, further comprising at least one bus circuitry that couples the common circuitry to the plurality of regions within the configurable integrated-circuit device.

4. The configurable integrated-circuit device of claim 3, in which the common circuitry further comprises a clock generator circuitry that provides at least one clock signal.

5. The configurable integrated-circuit device of claim 4, further comprising at least one port circuitry that facilitates communication between the at least two regions.

6. The configurable integrated-circuit device of claim 5, further comprising at least one dual-port memory circuitry coupled to the at least two regions.

7. The configurable integrated-circuit device of claim 6, further comprising input/output (IO) circuitry that facilitates communication between the common circuitry and circuitry external to the configurable integrated-circuit device.

8. The configurable integrated-circuit device of claim 7, in which the common circuitry is positioned at substantially the same distance from each region of the plurality of regions.

9. The configurable integrated-circuit device of claim 7, in which the common circuitry is positioned at substantially the same distance from each of the at least two regions of the plurality of regions.

10. A data-processing system including a configurable integrated-circuit device according to claim 4, the data-processing system further comprising at least one peripheral circuitry coupled to the configurable integrated-circuit device.

11. A data-processing system including a configurable integrated-circuit device according to claim 3, the data-processing system further comprising at least one peripheral circuitry coupled to the configurable integrated-circuit device.

12. A data-processing system including a configurable integrated-circuit device according to claim 2, the data-processing system further comprising at least one peripheral circuitry coupled to the configurable integrated-circuit device.

13. A data-processing system including a configurable integrated-circuit device according to claim 1, the data-processing system further comprising at least one peripheral circuitry coupled to the configurable integrated-circuit device.

14. A configurable integrated-circuit device, comprising:

a plurality of regions that each include configurable electronic circuitry; and

common circuitry that provides at least one signal to at least two regions of the plurality of regions,

wherein the common circuitry comprises at least one processor circuitry, and

the common circuitry and the at least two regions are positioned within the configurable integrated-circuit device so that the latencies of the at least one signal to each of the at least two regions tend to be equalized.

15. The configurable integrated-circuit device of claim 14, in which the common circuitry further comprises at least one memory circuitry that communicates with the at least one processor circuitry.

16. The configurable integrated-circuit device of claim 15, further comprising at least one bus circuitry that couples the common circuitry to the plurality of regions within the configurable integrated-circuit device.

17. The configurable integrated-circuit device of claim 16, in which the common circuitry further comprises a clock generator circuitry that provides at least one clock signal.

18. The configurable integrated-circuit device of claim 17, further comprising at least one port circuitry that facilitates communication between the at least two regions.

19. The configurable integrated-circuit device of claim 18, further comprising at least one dual-port memory circuitry coupled to the at least two regions.

20. The configurable integrated-circuit device of claim 19, further comprising input/output (IO) circuitry that facilitates communication between the common circuitry and circuitry external to the configurable integrated-circuit device.

21. The configurable integrated-circuit device of claim 20, in which the common circuitry is positioned centrally with respect to the plurality of regions.

22. The configurable integrated-circuit device of claim 20, in which the common circuitry is positioned centrally with respect to the at least two regions of the plurality of regions.

23. A data-processing system including a configurable integrated-circuit device according to claim 17, the data-processing system further comprising at least one peripheral circuitry coupled to the configurable integrated-circuit device.

24. A data-processing system including a configurable integrated-circuit device according to claim 16, the data-processing system further comprising at least one peripheral circuitry coupled to the configurable integrated-circuit device.

25. A data-processing system including a configurable integrated-circuit device according to claim 15, the data-processing system further comprising at least one peripheral circuitry coupled to the configurable integrated-circuit device.

26. A data-processing system including a configurable integrated-circuit device according to claim 14, the data-processing system further comprising at least one peripheral circuitry coupled to the configurable integrated-circuit device.

27. A programmable logic-device, comprising:

a plurality of regions that each include configurable electronic circuitry;

bus circuitry coupled to the plurality of regions; and

common circuitry coupled to the bus circuitry,

wherein the common circuitry comprises at least one processor circuitry, and

the common circuitry provides a signal to the plurality of regions through the bus circuitry, and

wherein the common circuitry and the plurality of regions are positioned within the programmable logic-device so as to improve the latencies of the signal to each region.

28. The programmable logic-device of claim 27, in which the common circuitry further comprises at least one memory circuitry configured to communicate with the at least one processor circuitry.

29. The programmable logic-device of claim 28, further comprising configurable interconnect circuitry coupled to each region.

30. The programmable logic-device of claim 29, further comprising input-output (I/O) circuitry coupled to the common circuitry.

31. The programmable logic-device of claim 30, in which the input-output circuitry is further coupled to the plurality of regions.

32. The programmable logic-device of claim 31, further comprising a memory controller circuitry adapted to communicate with memory circuitry external to the programmable logic-device.

33. The programmable logic-device of claim 32, in which the common circuitry further comprises a dual-port memory circuitry adapted to facilitate communication between a plurality of processor circuitries within the common circuitry.

34. The programmable logic-device of claim 33, which includes four regions, each region positioned in a quadrant of the programmable logic-device.

35. The programmable logic-device of claim 34, in which the bus circuitry includes a horizontal bus circuitry and a vertical bus circuitry that intersects the horizontal bus circuitry, wherein the intersection of the horizontal bus circuitry and the vertical bus circuitry overlaps at least in part with the common circuitry.

36. A data-processing system including a programmable logic-device according to claim 31, the data-processing system further comprising at least one peripheral circuitry coupled to the programmable logic-device.

37. A data-processing system including a programmable logic-device according to claim 30, the data-processing system further comprising at least one peripheral circuitry coupled to the programmable logic-device.

38. A data-processing system including a programmable logic-device according to claim 29, the data-processing system further comprising at least one peripheral circuitry coupled to the programmable logic-device.

39. A data-processing system including a programmable logic-device according to claim 28, the data-processing system further comprising at least one peripheral circuitry coupled to the programmable logic-device.

40. A data-processing system including a programmable logic-device according to claim 27, the data-processing system further comprising at least one peripheral circuitry coupled to the programmable logic-device.

41. A method of improving latency in a configurable integrated-circuit device, comprising:

providing the configurable integrated-circuit device;

partitioning the configurable integrated-circuit device into a plurality of regions that each include configurable electronic circuitry;

including within the configurable integrated-circuit device a common circuitry that provides at least one signal to at least two regions of the plurality of regions;

including in the common circuitry at least one processor circuitry; and

positioning the common circuitry and the at least two regions within the configurable integrated-circuit device so as to improve the latencies of the at least one signal to each of the at least two regions.

42. The method of claim 41, which further comprises including in the common circuitry at least one memory circuitry configured to communicate with the at least one processor circuitry.

43. The method of claim 42, which further comprises including in the configurable integrated-circuit device at least one bus circuitry adapted to couple the common circuitry to the plurality of regions of the integrated-circuit device.

44. The method of claim 43, which further comprises including in the common circuitry a clock generator circuitry adapted to provide at least one clock signal.

45. The method of claim 44, which further comprises including in the integrated-circuit device at least one port circuitry adapted to facilitate communication between the at least two regions.

46. The method of claim 45, which further comprises including in the integrated-circuit device at least one dual-port memory circuitry coupled to the at least two regions.

47. The method of claim 46, which further comprises including in the integrated-circuit device at least one dedicated input/output (IO) circuitry adapted to facilitate communication between the common circuitry and circuitry external to the integrated-circuit device.

48. The method of claim 47, which further comprises positioning the common circuitry at substantially the same distance from each region of the plurality of regions.

49. The method of claim 47, which further comprises positioning the common circuitry at substantially the same distance from each of the at least two regions of the plurality of regions.

50. A method of improving latency in a configurable integrated-circuit device, comprising:

providing the configurable integrated-circuit device;

partitioning the configurable integrated-circuit device into a plurality of regions that each include configurable electronic circuitry;

including within the configurable integrated-circuit device a common circuitry that provides at least one signal to at least two regions of the plurality of regions;

including in the common circuitry at least one processor circuitry; and

positioning the common circuitry and the at least two regions within the configurable integrated-circuit device so that the latencies of the at least one signal to each of the at least two regions tend to be equalized.

51. The method of claim 50, which further comprises including in the common circuitry at least one memory circuitry configured to communicate with the at least one processor circuitry.

52. The method of claim 51, which further comprises including in the configurable integrated-circuit device at least one bus circuitry adapted to couple the common circuitry to the plurality of regions of the integrated-circuit device.

53. The method of claim 52, which further comprises including in the common circuitry a clock generator circuitry adapted to provide at least one clock signal.

54. The method of claim 53, which further comprises including in the integrated-circuit device at least one port circuitry adapted to facilitate communication between the at least two regions.

55. The method of claim 54, which further comprises including in the integrated-circuit device at least one dual-port memory circuitry coupled to the at least two regions.

56. The method of claim 55, which further comprises including in the integrated-circuit device at least one dedicated input/output (IO) circuitry adapted to facilitate communication between the common circuitry and circuitry external to the integrated-circuit device.

57. The method of claim 56, which further comprises positioning the common circuitry at substantially the same distance from each region of the plurality of regions.

58. The method of claim 56, which further comprises positioning the common circuitry at substantially the same distance from each of the at least two regions of the plurality of regions.