Bias voltage generator usable with circuit for producing low-voltage differential signals

• US 6,531,892 B2
• Filed: 01/14/2002
• Issued: 03/11/2003
• Est. Priority Date: 09/05/2000
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Ghia, Atul V., Sodha, Ketan
• Primary Examiner(s): Chang, Daniel D.
• Application Number:
  US10/047,158
• Publication Number:
  US 20020060602A1
• Time in Patent Office: 421 Days
• Field of Search: 326/33, 326/44, 326/45, 326/49, 326/50, 326/87
• US Class Current: 326/50
• CPC Class Codes: H03K 19/018528 with at least one differential stage
• CPC Class Codes: H03K 5/151 with two complementary outputs
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end

Abstract

Described are systems for producing differential logic signals and circuits for biasing the voltages of the differential logic signals. These systems can be adapted for use with different loads by programming one or more programmable elements. One embodiment includes a series of driver stages, the outputs of which are connected to one another. The driver stages turn on successively to provide increasingly powerful differential amplification. This progressive increase in amplification produces a corresponding progressive decrease in output resistance, which reduces the noise associated with signal reflection. The systems can be incorporated into programmable IOBs to enable PLDs to provide differential output signals.

Claims

1. A bias voltage generator comprising:

a. a PBIAS line for controlling a p-channel transistor;

b. an NBIAS line for controlling an n-channel transistor;

c. a transistor for pulling up the PBIAS line;

d. a transistor for pulling down the PBIAS line;

e. a transistor for pulling up the NBIAS line;

f. a transistor for pulling down the NBIAS line;

g. a circuit for disabling the bias voltage generator and thereby pulling the PBIAS line to a logic one voltage level and the NBIAS line to a logic zero voltage level; and

h. a user controllable transistor enabled by a memory cell for programmably pulling up the PBIAS line.

2. The bias voltage generator of claim 1 further comprising a second user controllable transistor enabled by a second memory cell for programmably pulling up the PBIAS line.

3. The bias voltage generator of claim 1 further comprising a second user controllable transistor enabled by a second memory cell for programmably pulling down the PBIAS line.

4. The bias voltage generator of claim 3 further comprising a third user controllable transistor enabled by a third memory cell for programmably pulling down the PBIAS line.

5. The bias voltage generator of claim 1 further comprising a second user controllable transistor enabled by a second memory cell for programmably pulling up the NBIAS line.

6. The bias voltage generator of claim 5 further comprising a third user controllable transistor enabled by a third memory cell for programmably pulling up the NBIAS line.

7. The bias voltage generator of claim 1 further comprising a second user controllable transistor enabled by a second memory cell for programmably pulling down the NBIAS line.

8. The bias voltage generator of claim 7 further comprising a third user controllable transistor enabled by a third memory cell for programmably pulling down the NBIAS line.

9. The bias voltage generator of claim 1 wherein the PBIAS line controls a plurality of p-channel transistors and the NBIAS line controls a plurality of n-channel transistors.

10. The bias voltage generator of claim 1 wherein the p-channel transistors and the n-channel transistors provide drive current to output pins of an integrated circuit.

11. A bias voltage generator comprising:

a. a PBIAS line for controlling a p-channel transistor;

b. an NBIAS line for controlling an n-channel transistor,

c. a transistor for pulling up the PBIAS line;

d. a transistor for pulling down the PBIAS line;

e. a transistor for pulling up the NBIAS line;

f. a transistor for pulling down the NBIAS line; and

g. a circuit for disabling the bias voltage generator and thereby pulling the PBIAS line to a logic one voltage level and the NBIAS line to a logic zero voltage level;

h. wherein the circuit for disabling the bias voltage generator comprises;

a node for supplying a positive supply voltage to the transistors for pulling up the PBIAS line and the NBIAS line;

a node for supplying a ground voltage to the transistors for pulling down the PBIAS line and the NBIAS line;

a voltage supply terminal for providing a positive supply voltage;

a transistor for connecting the voltage supply terminal to the node for supplying a positive supply voltage to the transistors for pulling up the PBIAS line and the NBIAS line;

a transistor for connecting the voltage supply terminal to the PBIAS line; and

a memory cell controlling the transistor for connecting the voltage supply terminal to the node for supplying a positive supply voltage and the transistor for connecting the voltage supply terminal to the PBIAS line, wherein the memory cell turns on one and only one of the transistor for connecting the voltage supply terminal to the node for supplying a positive supply voltage and the transistor for connecting the voltage supply terminal to the PBIAS line.

12. A programmable bias-voltage generator adapted to provide first and second bias-voltage levels to respective first and second transistor control terminals of a differential amplifier, the differential amplifier producing an amplified differential output signal in response to a changing digital input signal, the bias-voltage generator comprising:

a. a first bias line connected to the first transistor control terminal and adapted to convey the first bias-voltage level;

b. a second bias line connected to the second transistor control terminal and adapted to convey the second bias-voltage level; and

c. at least one of a programmable pull-up circuit or a programmable pull-down circuit connected to the first bias line;

d. wherein the first bias-voltage level remains stable with changes in the digital input signal.

13. The programmable bias-voltage generator of claim 12, wherein the differential amplifier provides the differential output signal across first and second differential output terminals, expressing a logic one as a first current traveling in a first direction between the first and second differential output terminals and expressing a logic zero as a second current traveling in a second direction between the first and second differential output terminals.

14. The programmable bias-voltage generator of claim 13, wherein the first and second currents are proportional to the first bias-voltage level.

15. The programmable bias-voltage generator of claim 12, wherein the first transistor control terminal is the gate of a first transistor and the second transistor control terminal is the gate of a second transistor.

16. The programmable bias-voltage generator of claim 15, wherein the first transistor operates in saturation.

17. The programmable bias-voltage generator of claim 12, wherein the at least one of a programmable pull-up circuit or a programmable pull-down circuit connected to the first bias line is adapted to produce at least two bias-voltage levels on the first bias line, and wherein none of the at least two bias-voltage levels are power-supply voltage levels.

18. The programmable bias-voltage generator of claim 12, further comprising at least one of a second programmable pull-up circuit or a second programmable pull-down circuit connected to the second bias line, wherein the second, bias-voltage level remains stable with changes in the digital input signal.

19. The programmable bias-voltage generator of claim 18, further comprising at least one of a third programmable pull-up circuit or a third programmable pull-down circuit connected to the second bias line, wherein the second bias-voltage level remains stable with changes in the digital input signal.