High voltage generating circuit improved in parasitic capacitance of voltage-dividing resistance

• US 6,531,912 B2
• Filed: 02/23/2001
• Issued: 03/11/2003
• Est. Priority Date: 02/25/2000
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Katou, Kazuaki
• Primary Examiner(s): Cunningham, Terry D.
• Application Number:
  US09/790,491
• Publication Number:
  US 20010030364A1
• Time in Patent Office: 746 Days
• Field of Search: 327/534, 327/535, 327/537, 327/545, 327/546
• US Class Current: 327/536
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

The present invention provides a circuitry comprising: a first circuit for rising a voltage level, the first circuit having an output terminal connected to a high voltage output line for outputting a high voltage output; a comparator having an output terminal connected to an input side of the first circuit, the comparator further having a first input terminal and a second input terminal for receiving a reference voltage; and a voltage dividing circuit connected between the high voltage output line and a low voltage line having a substantially fixed lower potential than the high voltage output line, the voltage dividing circuit having an output node which is connected to the first input terminal of the comparator for outputting a divided voltage output and the voltage dividing circuit having at least a resistance between the output node and the high voltage output line, wherein a parasitic capacitance of the at least resistance between the output node and the high voltage output line is connected to the high voltage output line.

Claims

1. A circuitry comprising:

a first circuit for raising a voltage level, said first circuit having an output terminal connected to a high voltage output line for outputting a high voltage output;

a comparator having an output terminal connected to an input side of said first circuit, said comparator further having a first input terminal and a second input terminal for receiving a reference voltage; and

a voltage dividing circuit connected between said high voltage output line and a low voltage line having a substantially fixed lower potential than said high voltage output line, said voltage dividing circuit having an output node which is connected to said first input terminal of said comparator for outputting a divided voltage output; and

said voltage dividing circuit having at least one resistance between said output node and said high voltage output line,

wherein a parasitic capacitance of said at least one resistance between said output node and said high voltage output line is connected to said high voltage output line,

wherein said at least one resistance between said output node and said high voltage output line comprises a plurality of resistances connected in series, and

wherein parasitic capacitances of all of said resistances are connected to said high voltage output line.

2. The circuitry as claimed in claim 1, wherein said resistances have further parasitic capacitances connected to each other.

3. The circuitry as claimed in claim 1, wherein said plurality of resistances between said output node and said high voltage output line comprises two resistances connected in series, and parasitic capacitances of said two resistances are connected to said high voltage output line.

4. The circuitry as claimed in claim 1, wherein said first circuit comprises a booster circuit.

5. The circuitry as claimed in claim 1, wherein said low voltage line comprises a ground line.

6. The circuitry as claimed in claim 1, wherein resistances of said voltage dividing circuit comprises electrically conductive layers provided in an insulating layer extending over a semiconductor substrate, and said electrically conductive layer of said plural resistances between said output node and said high voltage output line is positioned over a well region in said semiconductor substrate and is isolated by said insulating layer, so that a parasitic capacitance of said plural resistances is formed between said well region and said electrically conductive layer, and said well region is electrically connected to said high voltage output line.

7. The circuitry as claimed in claim 6, wherein said well region has a first conductivity type and said semiconductor substrate has a second conductivity type and said semiconductor substrate is electrically connected to said low voltage line.

8. The circuitry as claimed in claim 7, wherein said low voltage line comprises a ground line.

9. The circuitry as claimed in claim 7, wherein said high voltage output line, said output node and said low voltage are provided over a top surface of said insulating layer.

10. The circuitry as claimed in claim 6, wherein said electrically conductive layers comprise polysilicon layers.

11. A circuitry comprising:

a first circuit for raising a voltage level, said first circuit having an output terminal connected to a high voltage output line for outputting a high voltage output;

a comparator having an output terminal connected to an input side of said first circuit, said comparator further having a first input terminal and a second input terminal for receiving a reference voltage; and

a voltage dividing circuit connected between said high voltage output line and a low voltage line having a substantially fixed lower potential than said high voltage output line, said voltage dividing circuit having an output node which is connected to said first input terminal of said comparator for outputting a divided voltage output; and

said voltage dividing circuit having at least one resistance between said output node and said high voltage output line,

wherein a parasitic capacitance of said at least one resistance between said output node and said high voltage output line is connected to said high voltage output line,

wherein said at least one resistance between said output node and said high voltage output line comprises a plurality of resistances connected in series, and a parasitic capacitance of at least a closest one of said resistances to said output node is connected to said high output voltage line, and wherein said plural resistances between said output node and said high voltage output line comprises two resistances connected in series, and a parasitic capacitance of a first one of said two resistances closer to said output node is connected to said high voltage output line and a parasitic capacitance of a second one of said two resistances closer to said high voltage line is connected to said low voltage line.

12. A circuitry comprising:

a first circuit for raising a voltage level, said first circuit having an output terminal connected to a high voltage output line for outputting a high voltage output;

a comparator having an output terminal connected to an input side of said first circuit, said comparator further having a first input terminal and a second input terminal for receiving a reference voltage; and

a voltage dividing circuit connected between said high voltage output line and a low voltage line having a substantially fixed lower potential than said high voltage output line, said voltage dividing circuit having an output node which is connected to said first input terminal of said comparator for outputting a divided voltage output; and

said voltage dividing circuit having at least one resistance between said output node and said high voltage output line,

wherein a parasitic capacitance of said at least one resistance between said output node and said high voltage output line is connected to said high voltage output line,

wherein said at least one resistance between said output node and said high voltage output line comprises first and second resistances, and

said first resistance comprises a first electrically conductive layer extending over a first insulating layer which extends over a well region in a semiconductor substrate, and said well region is electrically connected to said high voltage output line, and a parasitic capacitance of said first resistance is provided across said first insulating layer between said well region and said first electrically conductive layer; and

said second resistance comprises a second electrically conductive layer extending over a second insulating layer which extends over said first electrically conductive layer, and said second electrically conductive layer is electrically connected to said high voltage output line.

13. The circuitry as claimed in claim 12, wherein said well region has a first conductivity type and said semiconductor substrate has a second conductivity type and said semiconductor substrate is electrically connected to said low voltage line.

14. The circuitry as claimed in claim 13, wherein said low voltage line comprises a ground line.

15. The circuitry as claimed in claim 12, wherein said first and second electrically conductive layers comprise polysilicon layers.

16. A circuitry comprising:

a first circuit for raising a voltage level, said first circuit having an output terminal connected to a high voltage output line for outputting a high voltage output;

a comparator having an output terminal connected to an input side of said first circuit, said comparator further having a first input terminal and a second input terminal for receiving a reference voltage; and

a voltage dividing circuit connected between said high voltage output line and a low voltage line having a substantially fixed lower potential than said high voltage output line, said voltage dividing circuit having an output node which is connected to said first input terminal of said comparator for outputting a divided voltage output; and

said voltage dividing circuit having at least one resistance between said output node and said high voltage output line,

wherein a parasitic capacitance of said at least one resistance between said output node and said high voltage output line is connected to said high voltage output line,

wherein said voltage dividing circuit has at least a low voltage side resistance between said output node and said low voltage line, and a parasitic capacitance of said at least low voltage side resistance is connected to said low voltage line.

17. A high voltage generating circuit in a semiconductor device comprising:

a booster circuit having a first input terminal for receiving a clock signal and a second input terminal, and also said booster circuit having an output terminal connected to a high voltage output line for outputting a high voltage output;

a comparator having an output terminal connected to said second input terminal of said booster circuit, said comparator further having a first input terminal and a second input terminal for receiving a reference voltage; and

a voltage dividing circuit connected between said high voltage output line and a low voltage line having a substantially fixed lower potential than said high voltage output line, said voltage dividing circuit having an output node which is connected to said first input terminal of said comparator for outputting a divided voltage output; and

said voltage dividing circuit having at least one resistance between said output node and said high voltage output line, and said voltage dividing circuit having at least one low voltage side resistance between said output node and said low voltage line,

wherein a parasitic capacitance of said at least one resistance between said output node and said high voltage output line is connected to said high voltage output line, and a parasitic capacitance of said at least one low voltage side resistance is connected to said low voltage line,

wherein said at least one resistance between said output node and said high voltage output line comprises a plurality of resistances connected in series, and

wherein said parasitic capacitances of all of said resistances are connected to said high voltage output line.

18. The high voltage generating circuit in a semiconductor device as claimed in claim 17, wherein said resistances have further parasitic capacitances connected to each other.

19. The high voltage generating circuit in a semiconductor device as claimed in claim 17, wherein said plural resistances between said output node and said high voltage output line comprises two resistances connected in series, and parasitic capacitances of said two resistances are connected to said high voltage output line.

20. The high voltage generating circuit in a semiconductor device as claimed in claim 17, wherein said plural resistances between said output node and said high voltage output line comprises two resistances connected in series, and a parasitic capacitance of a first one of said two resistances closer to said output node is connected to said high voltage output line and a parasitic capacitance of a second one of said two resistances closer to said high voltage line is connected to said low voltage line.

21. The high voltage generating circuit in a semiconductor device as claimed in claim 17, wherein said low voltage line comprises a ground line.

22. The high voltage generating circuit in a semiconductor device as claimed in claim 17, wherein resistances of said voltage dividing circuit comprises electrically conductive layers provided in an insulating layer extending over a semiconductor substrate, and said electrically conductive layer of said at least one resistance between said output node and said high voltage output line is positioned over a well region in said semiconductor substrate and is isolated by said insulating layer, so that a parasitic capacitance of said at least one resistance is formed between said well region and said electrically conductive layer, and said well region is electrically connected to said high voltage output line.

23. The high voltage generating circuit in a semiconductor device as claimed in claim 22, wherein said well region has a first conductivity type and said semiconductor substrate has a second conductivity type and said semiconductor substrate is electrically connected to said low voltage line.

24. The high voltage generating circuit in a semiconductor device as claimed in claim 23, wherein said low voltage line comprises a ground line.

25. The high voltage generating circuit in a semiconductor device as claimed in claim 23, wherein said high voltage output line, said output node and said low voltage are provided over a top surface of said insulating layer.

26. The high voltage generating circuit in a semiconductor device as claimed in claim 22, wherein said electrically conductive layer comprises polysilicon layers.

27. A high voltage generating circuit in a semiconductor device comprising:

a booster circuit having a first input terminal for receiving a clock signal and a second input terminal, and also said booster circuit having an output terminal connected to a high voltage output line for outputting a high voltage output;

a comparator having an output terminal connected to said second input terminal of said booster circuit, said comparator further having a first input terminal and a second input terminal for receiving a reference voltage; and

a voltage dividing circuit connected between said high voltage output line and a low voltage line having a substantially fixed lower potential than said high voltage output line, said voltage dividing circuit having an output node which is connected to said first input terminal of said comparator for outputting a divided voltage output; and

said voltage dividing circuit having at least one resistance between said output node and said high voltage output line, and said voltage dividing circuit having at least one low voltage side resistance between said output node and said low voltage line,

wherein a parasitic capacitance of said at least one resistance between said output node and said high voltage output line is connected to said high voltage output line, and a parasitic capacitance of said at least one low voltage side resistance is connected to said low voltage line,

wherein said at least one resistance between said output node and said high voltage output line comprises first and second resistances, and

said first resistance comprises a first electrically conductive layer extending over a first insulating layer which extends over a well region in a semiconductor substrate, and said well region is electrically connected to said high voltage output line, and a parasitic capacitance of said first resistance is provided across said first insulating layer between said well region and said first electrically conductive layer; and

said second resistance comprises a second electrically conductive layer extending over a second insulating layer which extends over said first electrically conductive layer, and said second electrically conductive layer is electrically connected to said high voltage output line.

28. The high voltage generating circuit in a semiconductor device as claimed in claim 27, wherein said well region has a first conductivity type and said semiconductor substrate has a second conductivity type and said semiconductor substrate is electrically connected to said low voltage line.

29. The high voltage generating circuit in a semiconductor device as claimed in claim 28, wherein said low voltage line comprises a ground line.

30. The high voltage generating circuit in a semiconductor device as claimed in claim 27, wherein said first and second electrically conductive layers comprise polysilicon layers.