Bias method and circuit for distortion reduction
First Claim
1. A method of biasing a transistor by providing a biasing circuit, characterized by:
- generating a direct current (DC) signal proportional to a selected nonlinearity; and
using the DC signal to generate the bias voltage of the transistor at which the selected nonlinearity is zero.
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Abstract
The present invention provides a technique for selective cancellation of the 2nd-order or 3rd-order nonlinearity of a transistor. Any nonlinearity is a function of the bias voltage of a transistor. In many cases, this function is such that, at a particular bias voltage, nonlinearity is zero. The invention provides a bias circuit that generates the optimum bias voltage for a transistor at which its selected nonlinearity is zero. Mathematically, the nonlinearity can be represented by a sum of multiple components where some components have negative sign. The components are proportional to the DC currents of the transistor at bias voltages differing by a small amount. The bias circuit includes bias transistors that are scaled versions of the main transistor. Each bias transistor generates a DC current representing one of the components. The currents are combined according to the signs of the respective components to form a DC signal proportional to the selected nonlinearity. A feedback circuit senses the DC signal and generates the bias voltages of the bias transistors that force the DC signal to be zero. One of the bias voltages is applied to the main transistor resulting in cancellation of its selected nonlinearity. The system may be readily implemented using the integrated circuit technology such that the transistors of the bias circuit are closely matched to each other and to the main transistor. The distortion cancellation effect provided by the present invention exhibits low sensitivity to variations in the transistor processing and operational temperature.
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Citations
30 Claims
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1. A method of biasing a transistor by providing a biasing circuit, characterized by:
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generating a direct current (DC) signal proportional to a selected nonlinearity; and
using the DC signal to generate the bias voltage of the transistor at which the selected nonlinearity is zero. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A transistor biasing circuit, characterized by:
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a plurality of bias transistors each generating a DC current that is a portion of a DC signal proportional to a selected nonlinearity;
a combining circuit that combines the DC currents to form the DC signal; and
a feedback circuit to sense the DC signal and generate an input bias voltage of the bias transistors that cancels the selected nonlinearity. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A transistor biasing circuit for minimizing a signal distortion of a transistor, comprising:
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means for generating a direct current (DC) signal proportional to a selected nonlinearity; and
means for applying the DC signal to generate the bias voltage of the transistor at which the selected nonlinearity is zero. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30)
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Specification