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Bias method and circuit for distortion reduction

  • US 6,531,924 B2
  • Filed: 11/15/2001
  • Issued: 03/11/2003
  • Est. Priority Date: 04/18/2001
  • Status: Expired due to Term
First Claim
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1. A method of biasing a transistor by providing a biasing circuit, characterized by:

  • generating a direct current (DC) signal proportional to a selected nonlinearity; and

    using the DC signal to generate the bias voltage of the transistor at which the selected nonlinearity is zero.

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